Semiconductor device with reduced leakage current and method for manufacture the same

ABSTRACT

A semiconductor device with reduced leakage current and a method of manufacturing these reduced leakage current semiconductor devices are disclosed. The reduced leakage current semiconductor devices may be used for both static circuits and dynamic circuits. The reduced leakage current semiconductor devices reduce leakage current in the device when the node is not transitioning which occurs more than 95% of the time.

FIELD

The disclosure relates generally to the field of semiconductor devicesand in particular to a semiconductor device with reduced leakage currentand a method of designing these reduced leakage current semiconductordevices.

BACKGROUND

Semiconductor Integrated Chips (ICs) are crucial elements of allelectronic devices including computers and consumer electronics used ineveryday lives, large servers and machines that control many parts ofhuman lives everyday. For example ICs are used in critical defensemachines, machine that control the flow of information, the Internet,other communication networks and various communication mechanisms, etc.

Almost 95% of the ICs produced modernly are manufactured using a wellknown Complementary Metal Oxide Semiconductor (CMOS) process technology.CMOS has been the most used process technology in ICs for the past halfcentury and it is expected to be the technology of choice for manydecades in future.

CMOS technology has made remarkable and significant progress in lastcouple of decades. As predicted by Gordon Moore in 1965 (known asMoore's Law), CMOS manufacturing technology has progressed to a new NODEevery 2 years wherein CMOS transistor geometry is shrunk drasticallysuch that a given IC is shrunk to almost half size in less than 2 yearswhen re-designed and manufactured in next generation process. Thisimprovement results in lowering the cost of manufacturing ICs and/orincreasing the total amount of work that can be done by an IC.

In general, ICs manufactured using the newer technology are cheaper,more powerful and consume less energy. This trend has continued for manydecades and is expected to continue for many years in future. An exampleof the improvement is that, not long ago, a supercomputer required aentire building of space, required a dedicated mini power plant to powerand run air conditioner to cool all of the parts of the supercomputerand cost millions of dollars. Today, that same supercomputer fits in asmall backpack sleeve and is powered by a small mobile battery. ICs havebecome so miniaturized in size, have low power requirements and very lowcosts that ICS are now used in inexpensive toys and provide verysophisticated control, monitoring, audio visual or robotics functionsetc. Furthermore, current ICs are so reliable that they are integratedinto critical devices such as pacemaker. They are so critical thatentire country's defense infrastructure depends on them. The features,improvements and advantages of CMOS process technology has proven to bea gift to human kind and is expected to continue to be so for long time.

A CMOS device generally includes an N-type Metal Oxide Semiconductor(NMOS) transistor/device and/or a P-type Metal Oxide Semiconductor(PMOS) transistor/device (each of which is known as a MOS device or MOStransistor.) The NMOS and PMOS devices both work as voltage currentswitches or as voltage dependent current sources. When appropriatevoltage is applied at a control node, the switch is ON and current flowsbetween two terminals of the switch (the conducting switch) and whenanother voltage is applied at the control node the switch is OFF and nocurrent flows between the two terminals of the switch (thenon-conducting switch). Any MOS transistor has 4-terminals that includea “gate”, a “source”, a “drain” and a “body.”

Theoretically, for an NMOS device, a positive voltage on the gateterminal with respect to the voltage on the source terminal makes theNMOS act as an ON switch and the current flows from the source terminalto the drain terminal. Conversely, when voltage at the gate terminal issame as the voltage on the source terminal of the NMOS device, the NMOSdevice acts as an OFF switch and no current flows from the sourceterminal to the drain terminal or from drain terminal to the sourceterminal. Similarly, for a PMOS device, when a negative voltage isplaced on the gate terminal with respect to the source terminal, thePMOS device acts as an ON switch the current flows from the sourceterminal to the drain terminal or from drain terminal to sourceterminal. Conversely, when the voltage on the gate terminal is equal tothe voltage on the source terminal, the PMOS device acts as an OFFswitch and no current flows from the source terminal to the drainterminal or from drain terminal to the source terminal. The “body” nodein both NMOS and PMOS devices acts as a reservoir of mobile charges andhelps these devices act as switches.

Modern NMOS and PMOS devices have some residual current between thesource and the drain terminals even when the devices are supposedly OFF.There are other small currents in an actual MOS transistor that existand are inherent in the NMOS and PMOS device designs and are known“flaws”. These currents are collectively called “leakage” current or“static” current. Leakage or static current is an unavoidable flaw indevice behavior. Needless to say, in most cases, the leakage or staticcurrent is undesired and does not serve any meaningful purpose in an IC.Recently the leakage or static current has become significant percentageof the total current of the device.

With their switch like behaviors, CMOS transistors (NMOS and PMOS) arebest suited for digital technology and more than 95% ICs in the worldare designed using digital technology. In digital technology, allfunctions and computations are translated to only two states—“Zero” (0)and “One” (1), also called binary states. All logic functions,therefore, are constructed using binary states or binary logic. Logicgates that translate functions in binary logic are called Booleanfunctions or Boolean gates. These binary or Boolean gates are connectedphysically by wires to form a complete one-bit function or a multi-bitfunction. All computing functions are therefore converted to binary orBoolean functions using mathematics that follows Boolean algebra orbinary algebra (algebra with base 2).

A Boolean gate or Boolean function is implemented using CMOS transistorsthat are connected to each other through conducting wires. Each CMOStransistor works as switch that behaves as a voltage controlled currentsource. There are two types of CMOS transistors including a PMOS typetransistor and an NMOS transistor.

Even though energy consumption of electronic items (and hence ICs) hasbeen decreasing drastically and continuously, recently there isincreased emphasis on more power reduction in ICs because the totalnumber of these ICs has been growing at very fast pace but moreimportantly because energy is fast becoming a costly and scarce resourceglobally. The Semiconductor industry has increased its efforts inreducing power consumption in ICs with renewed vigor and focus in lastfew years. Reduced power consumption will become an increasinglyimportant design requirement of all ICs in future.

When logic functions are performed by ICs, currents flow from one nodeto another node which changes the voltage at each node thereby modulatethe binary value of each node. In CMOS, any transition of a nodeconsumes energy by conduction of current through an electric field.Thus, an IC consumes electrical energy to perform logic functions or fortransporting a logic value from one to other place. This is called“dynamic” energy or “active” energy. Dynamic Energy or active energyconsumed in unit time is called dynamic power or active power. A lot ofresearch is being done in the semiconductor industry today to reduceactive or dynamic power of ICs. Unfortunately, as mentioned earlier,practical CMOS devices and hence practical ICs also use “static” energyor “leakage” energy.

In recent years, the static energy/power used by an IC has become asignificant portion of total power consumed by the IC. In some cases,the static power can be as much as almost half of the total powerconsumed by the IC. To make matters worse, while dynamic power can bereduced by reducing the activity of nodes through development ofefficient computation algorithms, static or leakage power is hard toreduce and/or get rid of since the static or leakage power (from thestatic or leakage current) is inherent to the design of the MOS devicesthemselves.

Circuit designers connect NMOS and PMOS transistors to each other toform specific functions. Many basic Boolean gates are designed andimplemented from a “library” of Boolean functions. FIG. 1 shows ageneral structure of a CMOS logic gate or CMOS logic function inexisting CMOS Boolean technologies that includes a “pull up circuit” 101and a “pull down circuit” 102 with each circuit made of MOS transistorsconnected together to perform part of the Boolean computation to providethe complete desired Boolean computation for the gate. These pull up andpull down circuits are connected to “Supply 1” 105 and “Supply 2” 106,respectively. Supply 1 and Supply 2 are the necessary voltage source andvoltage sink nodes for currents to flow. “Supply1” 105 and “Supply2”also provide the voltage level references for logic “1” or Logic “high”and logic “0” or logic “low” for the functional gate, its internalnodes, input ports (103) and output ports (104).

Multiple CMOS Boolean gates can be connected together to form a morecomplex function with many inputs and many outputs. To connect one CMOSgate to another, the input of a “load” CMOS gate is connected to theoutput of “driver” CMOS gate. Many “inputs” of one multiple loads can beconnected to one output of a CMOS gate. Connection between CMOS gatesdepends on overall required logic function of the integrated CMOS gates.This general structure of a CMOS Boolean gate and CMOS Boolean functionhas been in existence and use for many decades in semiconductor designs.As described above, modern CMOS technology has an undesired component“the leakage current” that consumes power in any IC all the time unlessspecial methods and structures are adopted to reduce or eliminate thiscurrent component.

It is important to examine general behavior of all computation nodes inan IC as a whole to understand and tackle the issue of leakage power orstatic power in all modern ICs and in particular ICs designed andmanufactured using CMOS ICs since almost all ICs in modern world aredesigned and manufactured using CMOS.

A typical electrical behavior of all computation nodes, in any CMOS IC,is shown in FIG. 2 that shows one or more nodes' (184) behavior of afunctional block in active mode. It has been well established inindustry statistically that at any given clock interval, only 5%- to-15%of nodes make transition from logic ZERO to ONE or from logic ONE toZERO and rest of the nodes retain their old value and do not transition.Alternatively, if a computation node is looked at in the time domain(where time is measure in number of clock cycles), it would make atransition, on an average, only 5%-15% time (where time is measured bynumber of clock intervals). As shown in FIG. 2, Node 1, Node 2, . . . ,to Node n (184) make transitions only once in many clock cycles,otherwise they retain their logic status clock-cycle over clock-cycle.Transitions represent functional activity in a CMOS IC. This means mostnode don't participate in computation activities for more than 15% oftime.

Furthermore, as shown in FIG. 3, even within a given clock cycle, when anode transitions (202), the transitioning current occurs for a verysmall percentage of clock period (203). This shows that the actualtransition event's time duration is a very small percentage (typicallyless than 3% in ASICs and other ICs, 10% in ultra high end ICs such asmicroprocessors) of a clock period. Combining the two statics—that anode transitions in less than 15 clock cycles out of 100 clock cycles(maximum of 15%) and that within the clock cycle that it doestransition, the transition current itself flows for less than 10% timeof that clock period), it can be concluded that, a node spends almost98%-99% time waiting to do useful work (a transition activity) while itspends less than 2% time in actually doing useful work (making atransition).

As shown in FIG. 3, a leakage current or static current 204 of the nodeis always present in all nodes. This is not a new phenomenon. Thesestatistics and electrical behavior (of transition current being thereonly for a small percentage of time duration while leakage current isalways present for any given node) have always been present in all ICsusing CMOS technology. However, the leakage current, though alwayspresent, has been a very small percentage of the transition current andof the total current until recently. In modern ICs, leakage current is alarge percentage of transition and total current. Hence, the need toreduce or eliminate leakage current is more critical with modern ICsthan it was in the past.

As mentioned above, dynamic or active power consumption of ICs isproportional to the number of transitions made by all nodes in that IC.When the number of node transitions is less, the chip consumes lessdynamic or active power. IC designers use the concept of clock gating,for the less active node in an IC, to force the “clock” to NOTtransition. Unfortunately, the leakage or static current still flowsthrough all nodes whether transitioning or not. Therefore, dedicateddesign efforts need to be invested in reducing or eliminating theleakage or static current (or leakage or static power).

FIG. 4 illustrates general structures of current technologies that areused in the industry for leakage reduction. In these technologies,leakage current reduction is accomplished using a special signal called“Sleep” or “Standby” or something equivalent. This signal may be used inconjunction with low leakage MOS devices (PMOS 122 and NMOS 123 in FIG.4) in series with the main pull up and pull down paths and in serieswith the main computation circuit 121 to reduce leakage when the wholefunctional block may be inactive or less functional and not doing itsfull useful function. This specially configured sleep signal isgenerated using a specialized functional block(s) (a sleep monitoringblock). The sleep signal represents a time period when a functionalunit, many functional unit or the complete chip is guaranteed to beinactive or non-functional. Sleep signals and associated MOS devicesneed to be generated and designed for each sub-block, block or multipleof BLOCKs that needs to be switched OFF, independently. In thesedevices, special architectural features are designed to recognize suchopportunities and generate these “sleep” or “standby” signals. Suchopportunities when one of multiple blocks can be switched OFFsimultaneously are difficult to recognize and implement.

As shown in FIG. 4, a footer NMOS transistor 123 and a header PMOStransistor 122 is placed in series with the “Pull down circuit” and“Pull up circuit” respectively. The gate terminals of these footer andheader transistors are connected to special “sleep” or “standby” signalsfrom sleep/standby pin(s) 126, 127. For this circuit, the NMOS and PMOSdevices 122, 123 used for the footer and header are special “LowLeakage” transistors available from all semiconductor foundries. Once anappropriate logic level is asserted on sleep signals (Logic “HIGH” on“Sleep 1” and Logic “Low” on “Sleep 2”), the footer and headertransistors are off and the leakage of this functional block 121 isequal to the leakage of the footer and header devices 122, 123.

However, there are many limitations of the mechanism shown in FIG. 4.For example, the footer and header devices 122, 123 used in series ofmain functional pull down and pull up paths and the main computationlogic block 121 unfortunately slow down the main functionality of thelarge logic block 121. In particular, since in CMOS circuits, leakagecurrent and speed of operation are proportional to each other so thatincreasing the speed of the footer and header devices 122, 123 alsoincreases the leakage current thereby mitigating the very effect thesetechnologies are designed to create. Thus, the speed of a circuit thatuses the mechanism in FIG. 4 tends to be substantially slower.

Another limitation of the leakage reduction technology in FIG. 4 isthat, due to practical limitations, the header and footer devices 122,123 can only be used with large functional blocks and, in general, thelarger the block size, the smaller the probability to find appropriateopportunity to assert the sleep mode on the block. This means that theopportunities to reduce leakage current using these technologies arelimited, thus the effect of leakage reduction using such techniques isalso limited.

Yet another limitation of the leakage reduction technologies in FIG. 4is that the designer must design special functional blocks to generatethe “Sleep” signals. These blocks are tedious to design and requirechanges in the architecture of the IC which in turn affects the softwareand programming of the chip. Change in software requires changes incomplete eco-system in the manufacturing process and usage of the IC. Itis undesirable for any IC to need modifications in its usage environmentbecause it may limit the marketability of the IC itself. In addition,architectural changes in an IC also requires new functional verificationefforts for the IC that are very expensive. For these reasons IC designteams attempt to limit or eliminate changes that would requirearchitectural (hence software) modification. This limitation furtherreduces the probability of finding opportunities when a big functionalblock can be in “sleep” or “standby” mode.

FIG. 5 show that a functional unit or chip (IC) is in sleep mode (162)in between active mode (161) in time. To reduce leakage using “sleep” or“standby” signal, one need to maximize time interval represented by“sleep” mode 161. However, as explained above, doing so is a difficult,costly and inefficient task. As shown, the opportunities to put a blockin sleep mode are small which means small leakage current reductions.This figure represents statistical behavior of functional blocks (thatit is difficult to find opportunities to put a block in standby or sleepmode). This also makes sense from design philosophy point of view. Afunctional-block in an IC is designed and implemented to do useful work,not to be idle. If a functional block is idle most of the time, then theblock design and usage is inefficient, which in general is againstdesign and implementation methodologies used in industry because suchinefficiency result in expensive ICs that are commercially not verysuccessful.

FIG. 6 illustrates a device that uses sleep signals “SBB” and “SB” witha chain of inverters 141. These are sleep signal for this structure.These sleep signals cause virtual supply rails 146, 147, 149 and 150 tobe disconnected from the static (and actual IC) supply rails 148 and151. This disconnection causes virtual supplies and hence sources ofinverters connected to the appropriate supplies to drift to a differentvoltage than the static supply rails 148 and 151. This causes a negativegate biasing voltage to the MOS transistors that are supposed to be“OFF” and the leakage reduction in OFF transistors due to negative gatebiasing is substantial. However, the technique shown in FIG. 4 can beused only with a chain of inverters (not in a single inverter and notwith general logic functions) and hence is not useful of majority offunctional and circuit blocks in an IC. Moreover, the voltages onvirtual supply nodes are non-deterministic which means that charge onnodes in a block is not guaranteed to be retained when this structuregoes in “sleep” or “standby” mode. To mitigate the problem, the systemmay have a memory structure placed at important/relevant/all nodes sothat the logic is deterministic in sleep or standby mode. Therequirement of a memory bit for all important or relevant nodes or allnodes is too much overhead. The active power increase of the extrastructures is likely to be more than the saving realized in reduction ofleakage current. Also this technology is applicable only for a chain ofinverters which represents an insignificant percentage of logicfunctionality (if at all) within any IC. Virtual voltage beingnon-deterministic presents a reliability issue that needs to bemitigated with elaborate circuit structures otherwise the logic blockdriven by this structure may malfunction. This means that thistechnology is not implementable in practical commercial ICs.

It is desirable to provide a reduced leakage current semiconductordevice and method of manufacture that reduces leakage current when thedevice is not transitioning which occurs more than 95% of the time andit is to this end that the disclosure is directed.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates the general structure of a CMOS logic gate or CMOSlogic function using existing CMOS Boolean technologies;

FIG. 2 illustrates circuit behavior in an active mode and standby mode;

FIG. 3 illustrates circuit behavior in a given clock cycle;

FIG. 4 illustrates an existing technique for leakage reduction;

FIG. 5 shows that a functional unit or chip is in sleep mode in betweenactive mode in time;

FIG. 6 illustrates an existing leakage reduction technique that usessleep signals “SBB” and “SB” to a chain of inverters;

FIG. 7 illustrates a CMOS inverter;

FIGS. 8A1-8C illustrate schematic and cross section, respectively, of aNMOS device, a PMOS and an INVERTER;

FIGS. 9A-D illustrate four different states of an NMOS device;

FIG. 10 illustrates a normal IC development (design and implementation)process;

FIG. 11A illustrates an inverter with functionality divided in multiplesub blocks;

FIG. 11B illustrates voltage swings at interfaces between standardBoolean gates;

FIG. 12 illustrates functional sub-blocks of an inverter (or anyfunctional gate) using the reduced leakage current LOGIC (RLCL)technology;

FIG. 13A illustrates a voltage translator functionality inserted in thepath of signal propagation from one logic function to another logicfunction;

FIG. 13B illustrates Voltage translator circuit embedded in logic gatesand voltage swing at interface between the logic blocks;

FIG. 14A is a general functional block diagram of each gate of a reducedleakage current device or a reduced leakage current logic gate;

FIG. 14B-D are 3 different embodiments of implementation of the reducedleakage current device of FIG. 14A

FIG. 15 illustrates an INVERTER with reduced leakage current;

FIG. 16 illustrates a NAND2 gate with reduced leakage current;

FIG. 16 illustrates another embodiment of inverter with the reducedleakage current;

FIG. 17 illustrates a detailed block diagram level implementation of thegeneral circuit illustrated in FIG. 14A;

FIG. 18 is transistor level implementation of a NAND2 gate with reducedleakage current devices according to FIG. 17;

FIG. 19A illustrates another variation in block diagram levelimplementation of reduced leakage current;

FIG. 19B illustrate a transistor level implementation of an INVERTERcircuit with reduced leakage current devices according to scheme in FIG.19A;

FIG. 19C illustrates a transistor level implementation of a NAND2circuit with reduced leakage current devices according to FIG. 19A;

FIG. 19D illustrates schematic of a LOW Leakage INVERTER used in FIGS.19B-C;

FIG. 20A illustrates a block diagram level implementation of anothercircuit scheme of the reduced leakage current device;

FIG. 20B illustrates block diagram level implementation of still anothercircuit scheme of the reduced leakage current device (a variation ofFIG. 20A);

FIG. 21 illustrates a MOS transistor level implementation of a NAND2functionality using the circuit in FIG. 20;

FIG. 22 illustrates another block diagram level implementation of thereduced leakage current device;

FIG. 23 illustrates a MOS transistor level implementation of an inverterfunction according to the circuit diagram shown in FIG. 22;

FIG. 24 illustrates an implementation of a NAND2 functionality using UNand UP devices;

FIGS. 25A-D illustrates examples of implementations of the UN and UPdevices, respectively, on semiconductor wafers in semiconductor foundry;

FIG. 26 illustrates the general structure of a standard CMOS memory;

FIG. 27 illustrates more detailed connectivity and functional structureof standard CMOS SRAM memory implementation;

FIG. 28 illustrates details of a single bit cell of the RAM with thedetails of Word Line driver in a standard SRAM implementation;

FIG. 29 illustrates the leakage current paths related to memory bit cellin typical SRAM designs;

FIG. 30A illustrates the general structure of a memory with reducedleakage current devices;

FIG. 30B illustrates an implementation of an SRAM in which the reducedleakage current inverter is used for the wordline driver. Details of astandard SRAM bit cell are also shown;

FIGS. 31A and 31B illustrate two example of a dynamic functional logicblock in standard CMOS technology;

FIGS. 32A and 32B illustrate the circuit design of dynamic circuitsusing reduced leakage current circuits and RLCL technology;

FIG. 33 illustrates implementation of a reduced leakage current dynamicfunctional gate; and

FIGS. 34A and 34B illustrate an alternative implementation of a dynamicbuffer that is a reduced leakage current dynamic functional gate.

FIG. 35A-B are flow chart level description of method and functioning ofreduced leakage current devices

DETAILED DESCRIPTION OF EMBODIMENTS

The disclosure is particularly applicable to a CMOS device with leakagecurrent reduction and method of manufacture and it is in this contextthat the disclosure will be described. It will be appreciated, however,that the leakage power reduction technique illustrated and describedbelow has greater utility since it can be applied to other types ofsemiconductor devices and may be implemented in other ways that arewithin the scope of the disclosure.

The leakage current reduction and method of manufacture uses the conceptof applying negative DETERMINISTIC gate voltage to MOS transistors toreduce leakage current. Furthermore, a new concept is introduced that isautomatic, self monitored, and fully contained at the CMOS gate level.This means that each logic gate monitors and reduces its leakage currentwhen not switching itself. Furthermore, no external control signal isrequired to monitor or control the leakage current of a logic gate or alogic block. As a result a very easily adoptable and very widely useablebasic logic cell library and memory blocks or memory compiler can bedesigned and implemented. This library is similar to the standard cellCMOS cell library that is widely used in industry currently but providesa very important and needed feature of significantly reduced leakagepower. Since all required apparatus and methods to deterministicallyapply negative gate voltage selectively to leaky MOS transistors areself contained within the logic cell gate, this technology is widelyapplicable and easily adoptable in all semiconductor ICs. This is a Inthe disclosure, the CMOS gate is divided into its separate nativefunctions and the device incorporates new functional units to reduceleakage current. These functions have been separated in such a way thatthe Logic gate still appears almost identical to the classical CMOSlogic gate to RTL, manufacturing rules and constraints and EDA tools.Only a very small modification is required to the implementationmethodology to incorporate this technology. All features of a classicaland prevalent CMOS logic gate are practically preserved at the boundaryof the new CMOS Logic gate with reduced leakage current so that thereduced leakage current device is easily adoptable in all CMOS ICs.

Yet another concept introduced in this invention is related to theelectrical and speed performance of CMOS gate. It should be recognizedthat in a CMOS IC, where Boolean gates are connected to each other, thetransition of an output from LOGIC ZERO to LOGIC ONE or vice versadoesn't require an output signal (which is input to another CMOS Booleangate) to fully transition from one Supply Rail to another Supply rail.Due to embedded characteristic of a CMOS gate, input of a gate is atLOGIC HIGH if it is slightly HIGHER than the “INPUT HIGH THRESHOLD” ofthat CMOS gate. Similarly the input is LOGIC LOW if it is slightly LOWERthan the “INPUT LOW THRESHOLD” of that CMOS gate. It is not necessarythat the MOS device that performs electrical charging and dischargingfunction at high speed should also provide the LOGIC VOLTAGE LEVELtranslation from INPUT TO OUTPUT. In this invention the electricalcharging/discharging (or voltage translation) functions are separatedfrom LOGIC translation functions wherever these voltage translationfunctions wherever appropriate.

FIG. 7 shows schematic of the most basic CMOS Boolean logic function—aninverter. The inverter has a PMOS device 223 and a NMOS device 224 thatare connected together. In more detail, the PMOS device or transistor(223) is connected, at its drain, to an NMOS device transistor 224 and,at its source, to Supply1 (vdd) (221). The NMOS device or transistor 224is connected, at its drain, to the PMOS device 223 and at its source toSupply2 (vss) (222) as shown in FIG. 7. The gates of both the PMOS andNMOS devices 223, 224 are connected to an input node “In” (225) and thedrains of the PMOS and NMOS devices are connected to an output node“Out” 226. Nodes “In” (225) and “Out” (226) are the input and output,respectively, of the inverter. When input “In” has a voltageapproximately equal to the voltage at “Supply1” or Vdd or “Logic High”,the PMOS transistor is turned OFF and NMOS transistor is turned ON whichcauses current to flow from output node to Supply 2(Vss). Supply 2 worksas a current sink and is typically at ZERO volts. As a result, the flowof current from the output node to Vss causes the voltage at output nodeto be approximately equal to ZERO volts which is “LOGIC ZERO” or “LOGICLOW”. Similarly when the voltage at input node (225) is approximatelyequal to voltage at node “Supply2” or “vss” or “LOGIC ZERO”, the NMOSdevice is turned OFF and PMOS device is turned ON which causes currentto flow from “Supply 1” or “Vdd” to output node “Out” (226) whichcharges the output node “Out” to voltage approximately equal to “Vdd”which is “LOGIC HIGH” or “LOGIC ONE”. In summary when input is LOGIC LOW(which is approximately equal to voltage at Vss) then output is LOGICHIGH (which is approximately equal to voltage at Vdd) and when input isLOGIC HIGH (which is approximately equal to voltage at Vdd) then outputis LOGIC LOW (which is approximately equal to voltage at Vss) which isthe well known operation of an inverter.

While the inverter appears to be a very simple device with a very simpleoperation, many assumptions, electrical activities and functionalitiesof various nodes in the inverter (as in all Boolean CMOS gates) arehidden and are taken for granted by electrical designers. In thisinvention the hidden behavior, activities, properties andfunctionalities of inverter (or of any CMOS logic gate) and its internalnodes are used and modified to reduce leakage in CMOS circuits. Thesehidden behaviors, activities, properties and functionalities arediscussed in later sections.

FIGS. 8A1-C illustrates a schematic and cross sections of a NMOS deviceand a PMOS device and a cross section of an inverter, respectively. Thefeatures exhibited by an inverter are exhibited by all CMOS Booleangates. When designing any alternatives to this classical CMOS Booleangate structure, one needs to preserve these subtle and hidden features,behaviors and properties of the CMOS Boolean gates that providesubstantial practical benefits in a real practical CMOS IC.

The reduced leakage current technology exploits the multi functionalability of the connectivity and presence of NMOS and PMOS devices in aCMOS structure to reduce leakage significantly.

FIG. 8A1 illustrates a schematic of PMOS device that has a source/drainterminal 276, a P-substrate terminal 277, a drain/source terminal 278and a gate terminal 279. FIG. 8A2 illustrates cross section of the PMOSdevice in which the PMOS device is fabricated on a N-substrate or anN-well. The PMOS has two doped P+ diffusions 286, 289 that are implantedin a N-substrate or N-well 287. These two function as the source ordrain ports 283, 284 of the PMOS device and these two areinterchangeable in circuit usage. A non conducting Silicon oxide 282 isformed aligned with the ends of source and drain implants as shown. Aconducting Poly Silicon gate 281 is deposited aligned with the nonconducting oxide 282. The source and drain nodes (289, 286) aremetalized to provide conducting source/drain nodes 280, 283. To connectthe substrate 287 to appropriate voltage supply, a highly doped N+implant 1286 is formed in substrate 287 and the metallization is done ontop of this implant to form a conducting substrate node 284. These fournodes (gate (281), source/drain (280, 283) and substrate (284)) areavailable to circuit designers for appropriate usage.

FIG. 8B1 illustrates a schematic of an NMOS device that has fourterminals—a source/drain 272, a P substrate 273, a drain/source 274 anda gate 275. FIG. 8B2 illustrates the cross section of a the NMOS devicethat is fabricated on a P substrate or an P+ well. The NMOS device has 4nodes. Two heavily doped N+ diffusions (299, 296) are implanted in alightly doped P-type substrate 297 (also called P-substrate). These twofunction as the source or drain ports of the NMOS device. These two areinterchangeable in circuit usage and any of these two (299, 292) canfunction as source or drain ports. A non conducting Silicon oxide 292 isformed aligned with the ends of source and drain implants as shown. Aconducting Poly Silicon gate 291 is deposited aligned with the nonconducting oxide 292. Source and drain nodes (299, 296) are metalized toprovide conducting source/drain nodes 290, 293. To connect the substrate297 to appropriate voltage supply a highly doped P+ implant 1296 isformed in substrate 297 and the metallization is done on top of thisimplant to form a conducting substrate node 294. These four nodes (gate(291), source/drain (290, 293) and substrate (294)) are available tocircuit designers for appropriate usage.

When used together in an inverter as shown in FIG. 8C, a substrate node256 of the NMOS device is connected to a supply node 255 with lowestvoltage called VSS or GND (generally at ZERO Volts). One of thesource/drain nodes (260 or 262) of the NMOS device is also connected tothe same supply node with the lowest voltage and this node becomes thesource node of the NMOS, while the other node becomes drain node of theNMOS as shown in FIG. 8C. Similarly for the PMOS device, a substratenode 266 is connected to a supply node 250 with highest voltage calledVDD or VCC (which has different voltage value in differenttechnologies). A source node 265 of the PMOS device is also typicallyconnected to the same supply node VDD or VCC. In an inverter, the drainnodes of NMOS 262 and PMOS 263 are connected together as shown in FIG.8C to form an output port 253 of the inverter. Similarly the gate nodes251, 254 of NMOS and PMOS are connected together to form an input port252 of the inverter.

FIGS. 9A-D illustrates four different states of an NMOS device. The MOSconduction and leakage mechanisms can be understood from functioning ofan NMOS device. As shown in FIG. 9A, an NMOS device has its substrateand source node tied to 0 Volt (VSS or GND) which is the supply nodewith lowest voltage (323). The NMOS device is now configured and capableto draw electrons from VSS to form a conducting channel due to thisconnection (323). If the voltage on a Gate node 322 is lower than afixed voltage called Threshold voltage (Vt) compared to voltage atsource (322) (that is Vss), the conducting channel is not formedunderneath the gate (325) and the NMOS device is theoretically OFF. Ifthe Gate node 322 is driven to a voltage greater than Vt (332) and thedrain node is still at same voltage as the source (0V in this case) asshown in FIG. 9B, electrons are drawn from substrate underneath the Gatedue to Electric field through the gate oxide (336) and form an uniformconduction channel (335). Though this channel is formed and ready toconduct there is still no current between source and drain nodes becausethere is no voltage gradient between drain and source. FIG. 9C shows thenext stage. To make the NMOS conduct, the voltage on drain node (341) israised above the voltage on source node 343 as shown in FIG. 9C. Now theNMOS transistor is ON and conducting current from drain to sourceterminals. As the voltage on drain terminal increases above sourceterminal, the current in NMOS transistors increases till it saturates.Once saturated the NMOS has reached its maximum current for a givengate-source voltage and the current can increase no more.

FIG. 9D shows the OFF transistor from FIG. 9A but in a practicalcondition (where Gate voltage Vg is less than Vt and drain voltage isVdd or other high voltage). The gate voltage is lower than Vt (352) andthe NMOS device should be OFF but a practical device exhibits non-idealbehavior. In particular, underneath the gate, mobile charges (electronsin this case) are generated due to thermal energy inside the channel 355thereby forming a channel of thermal mobile charges. If the drainvoltage is greater than voltage on the source node, current flowsbetween source and drain nodes causing leakage current. The leakagecurrent is larger at larger drain-source voltage. Similarly the leakagecurrent is larger at higher temperature.

This leakage current is mostly undesired in CMOS ICs.

The operation of the PMOS device is similar to the NMOS device exceptthat the channel formed in PMOS is that of positive mobile charges(called holes), the voltage on substrate and source is VDD and the gatevoltage is negative as compared to source voltage for the PMOS toconduct. However, leakage mechanism is similar in that thermal mobilecharges form unwanted conduction channel and cause the PMOS transistorto leak current.

In practice in a CMOS gate, one or more of PMOS transistor or one ofmore of NMOS transistor is theoretically always OFF, but has leakagecurrent. Thus, all OFF MOS transistors in digital ICs have leakagecurrents. As stated earlier, in modern CMOS ICs, leakage is a largepercentage of total current in ICs which is undesired. It is a known andunderstood fact in the industry that the leakage current is linearlyproportional to the voltage between drain and source nodes of a MOStransistor and exponentially proportional to the voltage between gateand source when magnitude of Gate-Source voltage is below Vt (calledsub-threshold condition for MOS device). This exponential behaviorcontinues even when voltage on gate node is lower than voltage on sourcenode for NMOS or when the voltage on gate node is higher than thevoltage on source node of a PMOS transistor (the NEGATIVE GATE Voltage).When the gate voltage on MOS is lower than the source voltage or whenthe gate voltage in a PMOS is higher than the gate voltage, this iscondition of NEGATIVE GATE VOLTAGE. Since leakage current decreasesexponentially in sub-threshold region of the gate voltage (gate voltagesmaller than threshold voltage or Vt) even when the gate voltage-sourcevoltage is negative, applying negative gate voltage is a very effectiveway of reducing leakage current exponentially in MOS devices and hencein CMOS ICs.

This known property of exponential reduction in leakage current in MOStransistors below Vt (in particular negative Vt) is used in this currentinvention. New circuit design methods and circuit design topologies areinvented to apply negative gate-source voltage (also called Negativegate voltage biasing or simply negative gate biasing) to MOS transistorsthat have high leakage in standard CMOS gates but are required to beused in ICs to achieve speed and performance. Details of these methodsand circuit designs are discussed in later sections.

FIG. 10 illustrates a normal IC development (design and implementation)process. In the process, three independent user inputs are mixed anditerated by Electronic Design Automation (EDA) tools 388 to produce aphysical database in graphical format that is converted by themanufacturing house (“semiconductor foundry” or “Foundry”) into aphysical IC that finally gets used in a system board to perform aspecific electronic function. Specific description of functionality andconnectivity is generated by a system design engineering team based onsystem requirement 381 provided to IC design engineers. The IC designengineers translate these requirements and connectivity into knownRegister Transfer Logic (RTL) (383) for the intended IC. RTL is softwarelike description of IC's functionality and connectivity, written in aHardware Description Language (or HDL). Using EDA tools (388), the RTLis mapped to a Physical IP Library (384) to produce an intermediateformat called netlist that describes connectivity of basic functionalblocks from Physical IP library (384) to form the complete designedfunctionality of the IC. Physical Intellectual Property (IP) Libraryconsists of basic functional blocks that can be connected together toform a hardware function. As mentioned, most ICs are CMOS based. Hencemost Physical IP Library used in the industry is also CMOS based. Usingmanufacturing rules and constraints provided by the manufacturingfactory (semiconductor foundry) (392) and the Physical IP library (384),and according to the rules and mechanism of the implementationmethodology 387 as designed by implementation engineers, the EDA toolproduces the graphical patterns and database or Physical database (389).This physical database is then processed by software tools and (mostlyrobotics) machines of the foundry to produce the physical siliconintegrated chips (IC) 390 that gets used in a system board (382). Ingeneral RTL (383), Physical IP library (384), manufacturing rules andconstraints (392), and EDA tools and Implementation methodology (387)are provided by different companies or different teams.

Because of high cost of Manufacturing of CMOS ICs, the companies thatmanufacture and develop new CMOS ICs has consolidated in recent yearsand only a few companies in the world have modern semiconductormanufacturing factories. Modern Semiconductor manufacturing involvesvery high skilled engineering and scientific manpower, machines andinfrastructure. Because of highly sensitive and secretive manufacturing,materials, methods, flow and procedures it is not practical for ICdesigners to cause changes in manufacturing rules and constraints. Thismeans these rules and constraints are generally rigid and inflexible.These rules and constraints are provided to IC design engineers bysemiconductor foundries.

The RTL (383) depends on the requirement from the customer or thesystem. Though an RTL designer can request changes in functionality andconnectivity from system engineering team, in practice such changerequests are avoided because of perturbation such changes may cause inthe customer's systems, software and usage chain. Since such changerequests are expensive to incorporate at system and software level,these are avoided also because of business reasons. This means RTL isalso generally a rigid and inflexible to a large extent for a given IC.Any major change in RTL is avoided in practice. It is important to knowthat generally an IC is owned by the company or team that owns RTL.Therefore, any quality improvements or reduction/elimination inshortcomings or limitations are therefore addressed in implementationmethodology (387), Physical IP Library (384) and EDA tools (388). Amongthe three, use of Physical IP Library to eliminate issues or makeimprovements is preferred because of lower cost of making changes in aPhysical library. Also because changes in Physical IP Library arecontained within the library and very little or no effects are caused onany other part of the IC construction process.

The reduced leakage current device and method of manufacture is acircuit technology that can be implemented to form a Physical IPlibrary. Furthermore, no effects are caused on RTL, EDA tools ormanufacturing rules and constraints. In addition, very little (almostnegligible) effect is caused on “Implementation methodology.” Thereduced leakage current device and method of manufacture also may beused with and is compatible with most leakage reduction technologiesthat are based on architectural or manufacturing features. It reducesleakage significantly even in ICs that already use one or other leakagereduction technologies. Because of these advantages, the reduced leakagecurrent device and method of manufacture can be easily implemented inall CMOS ICs.

As mentioned earlier an inverter of FIG. 7, is very simple inconstruction and functionality at a high level, but it has many hiddenfeatures, functionalities, activities and properties. For purpose ofthis invention, these are revealed and analyzed below:

-   -   (i) Supply 1 and Supply 2 (the “Vdd” and Vss”) perform many        functions in the inverter:        -   a. Vdd works as current source. All nodes inside the logic            gate derive current from Vdd. Similarly Vss node works as a            current sink. All current from the logic gate are sinked to            Vss.        -   b. Vdd is a representation of “LOGIC HIGH” or “LOGIC ONE”            and Vss is a representation to “LOGIC ZERO” or “LOGIC LOW”.            This means any node that is approximately equal to Vdd in            voltage is at “LOGIC 1” or “LOGIC HIGH” and any node that is            approximately equal to Vss is at “LOGIC 0” or “LOGIC LOW”.            It must be noted that equality of Vss to “LOGIC 0” (or “0”)            and equality of Vdd to “LOGIC 1” (or “1”) is not a            requirement for Boolean (or binary) logic computation.            Because of its simplicity, this has been the preferred way            of implementation in CMOS ICs.        -   c. Vdd and Vss are also the reference voltage for input            (“In”) and output (“Out”) nodes. The input is driven to Vdd            or Vss (or approximate voltage levels) and output            transitions to the same voltages (approximately equal to Vdd            and Vss). This means output node of a Boolean gate can be            connected to the input node of another Boolean gate with any            conductor without any interface elements in between. This is            a remarkably powerful property of CMOS that makes it very            easy to connect any number of logic blocks of any size and            any functionality to other without any issues and limitation            as long as designed functionality is achieved after            integration of these blocks. This means IC designers can            worry about the connectivity for functionality alone. There            is no need to worry about compatibility of connections.    -   (ii) At any given time in an inverter, only a PMOS device or an        NMOS device is ON. This electrical activity concept is followed        in all Boolean gates (with any functionality) that have Pull up        and Pull down circuits connected to any given output since only        one of the Pull up or Pull down circuit is ACTIVE thereby        pulling the output to LOGIC ONE or LOGIC ZERO. Active or        transition current does not flow from Supply 1 (Vdd) to Supply 2        (Vss) except for the limited duration when the output of the        gate transitions from one logic value to another. This means        that the output of a Boolean gate always transitions to a        voltage equal to Vdd or Vss in steady state (some error in this        equality occurs due to leakage current or noise).    -   (iii) The inputs and output of a Boolean gate are virtually        connected to Vdd and Vss without designer making special efforts        so that the output of a CMOS Boolean gate is universally        compatible to inputs of any other Boolean gate.    -   (iv) A PMOS device pulls positive charges from Supply 1 or Vdd        to form a channel when it switches ON to conduct current.        Similarly the NMOS device pulls negative charges from Supply 2        or Vss to form a channel when it switches ON.    -   (v) The N-substrate or N-well where a PMOS device is located on        a silicon wafer connects to the highest voltage which is        generally Supply 1 or Vdd and the P-substrate or P-well where        NMOS devices is located on the silicon wafer connects to the        lowest voltage on the IC which is generally Supply 2 or Vss. The        source terminals of PMOS and NMOS devices are also connected to        the same nodes Vdd and Vss in general in most CMOS ICs.    -   (vi) When the input transitions between logic values, the output        transitions in a reverse order for an inverter. The output is        then held to the transitioned LOGIC value by the same device        that conducts current for that transition. This means that the        same MOS devices that provide means for logic computation also        work as driver for connectivity (a wire) that connects the        output of this gate to input of other gates. For example, when        input transition from LOGIC LOW to LOGIC HIGH, the output        transitions from LOGIC HIGH to LOGIC LOW and the NMOS device        switches ON and conducts current from output node to Vss to make        this transition happened. Additionally, if another logic gate is        connected to the output node (“load”), this same NMOS would        conduct current from input of this connected gate “load” thereby        transitioning the input of the “load” gate. This additional        functionality of MOS devices in the “driver” CMOS gate provides        ease of use implementation of CMOS technology.    -   (vii) Inputs of a MOS gate are non-conducting. This means that        no static current flows between the input of a “load” CMOS gate        and output of a “driver” CMOS gate in steady state. Only stored        mobile charges are pulled or provided by the “driver” gate to        the “load” inputs. This means any number of “load” CMOS gate can        be connected to output of a CMOS gate without loss of accuracy        as long as enough time is available for making the transition of        load inputs. In practice the number of loads is limited to        achieve good speed of transition.

The CMOS INVERTER of FIG. 7 can therefore be seen as a circuit blockconsisting of a group of functional blocks connected together as shownin FIG. 11A. These functional blocks are input receiver (5113), outputdriver (5114), logic computer (5111) and noise filter (5112). Powersupplies “Supply 1” or “Vdd” 5115 and “Supply 2” or “Vss” 5116 providethe current source and sink functionalities along with being referencefor compute, compare, noise and other necessary functions.

Amazingly, as shown in FIG. 7, in a standard CMOS process, all of thesefunctions are performed by a simple entity (227) consisting of asingular PMOS (223) and a singular NMOS (222) in an inverter in standardCMOS process.

In standard CMOS logic gate, the input and output signals transitionbetween two voltage rails Vdd and Vss as shown in FIG. 11B. Because ofthis, when two or more logic gates are connected together, the wiresconnected between the logic gates also transition between the samesupply rails Vdd and Vss. All MOS transistors that provide variousfunctionalities are also connected to the same supply rails Vdd and Vssas shown in FIG. 7 and FIG. 11A.

FIG. 11B shows voltage transition of signals connecting multiple Logicfunctions in standard CMOS process. A set of output and inputs signalsor wires 5121, 5123, 5124 transition between supply-rails “Vdd” and“Vss”, the same supply rails that the logic function gates 5122, and5128 are connected to. Uniformity of supply rails for connectingtransistors and reference for input and output signal swing providesease and simplicity of operation and implementation. However, thisuniformity becomes a limitation and causes high leakage in high speedMOS transistors in standard CMOS logic circuits.

FIG. 12 illustrates general construction and functionalities of aninverter (or any other logic function gate) using leakage reductiontechnology of this invention. New sub blocks have been added to thesub-blocks of FIG. 11A to accomplish reduction in leakage current. Thenew functionality sub-blocks are “Voltage translator” 5082, “Currentcontrol decision circuit” 5086 and “Current Control circuit” 5085. Otherfunctional sub-blocks of FIG. 11A of standard CMOS INVERTER (or anystandard CMOS functional gate) remain same as FIG. 11A and perform allthe necessary standard functions of CMOS gate described earlier, namelyLogic computer (5081), Noise filter (5087), output Driver (5083) andInput receiver (5084). Two new supply rails are added “Vddsp” and“Vsssp” making the number of supply rails to be 4 (as compared to 2 in astandard CMOS Boolean logic gate). Supply1 (5090) and Supply2 (5091) aretwo “voltage high” supply rails (Vddsp and Vdd) and Supply3 (5092) andSupply4 (5093) are two “voltage low” supply rails (Vss and Vsssp). Thequad supply rails consisting of dual “Voltage High” and dual “VoltageLow” (5090, 5091 and 5092, 5093, respectively) are used to providevoltage references for generating DETERMINISTIC negative gate voltagesto MOS devices and do other necessary functions required by the logicfunction gate.

All functionalities and features of a functional logic gate arepreserved in the technology as per this invention with added featurethat each functional logic gate has substantially lower leakage currentthan an equivalent standard CMOS gate. This reduction in leakage currentis achieved by circuit design technology that causes DETERMINISTICnegative gate-source voltage to MOS transistors with high leakagecurrent without need for any external control signal. All functionalgates are self sufficient in achieving this feature in addition topreserving all required functionality of a standard CMOS functionalgate.

It is important to note that CMOS circuits can be commercially viableonly when its performance and behavior can be predicteddeterministically in all conditions of environment, manufacturing, andmaterial properties. Since voltage supply on different terminals of aMOS transistors affects behavior and performance significantly, mostly,a CMOS circuit technology is not of use commercially if deterministicvoltages cannot be applied to all terminals of MOS transistors.

Also, when a circuit element or block requires external control signalto exhibit its properties, its usage and applicability are limited.Leakage reduction in CMOS circuits also has same property. Hence, a selfcontained automatic leakage reduction technology is essential formaximizing the impact.

Technologies described in this invention achieve all desired properties.Deterministic MOS current behavior is achieved by using deterministicvoltages and voltage references and circuit apparatus to utilize thesevoltages and references appropriately. Circuit design, apparatus andmethods eliminate need for any external control signal. Thus CMOScircuits constructed with this technology provide leakage reductionalways, when not switching without help of external control signals.

The “Voltage translator” block 5082 in FIG. 12 does voltage translationof input and/or output signals from one supply rail to another supplyrail. For example, it can be implemented to apply Vddsp on gate of aPMOS transistor whose source is connected to Vdd supply rail when thePMOS is supposed to be OFF, thus causing negative gate-source voltage toPMOS transistor(s), assuming Vddsp was a higher voltage than Vdd.Similarly, it can be implemented to apply a voltage Vsssp on gate of anNMOS transistor whose source is connected to Vss supply rail when theNMOS transistor(s) is supposed to be OFF, thus causing a “negative”gate-source voltage to NMOS transistor(s) assuming Vsssp is a lowervoltage than Vss. In general, this functional block can translate inputsignal or output signal from one supply rail to another. Furthermore itcan translate an internal gate, source or drain signals from Vdd toVddsp or vice versa or from Vss to Vsssp or vice versa. Thisfunctionality is in addition to the functionality of a standard CMOSlogic gate of computing output voltage to be LOGIC HIGH or LOGIC LOW asa function of combination of inputs and the logic functionimplementation. The “Current Control Circuit” 5085 provides control ofleakage current when the output is not switching in addition to controlof current for switching the output depending on the inputs and logicfunctions. “Current control decision circuit” 5086 monitors the behaviorof the “Current Control Circuit” 5085 by monitoring how and when the“current control circuit” 5085 should be in operating condition forreduced leakage current, or operating condition for high switchingcurrent. It should be noted that such monitoring may have to be appliedseparately for all PMOS and NMOS transistors in the functional gate orthey can all be driven by a single control or a combination of the two.

In other possible embodiments, number of supply rails can be changedfrom 4 to 3. Any of the 4 supply rails can be eliminated depending onwhether leakage reduction is to be realized in both PMOS and NMOS orboth Pull up and Pull down or only in Pull up or Pull down (or only inPMOS or NMOS).

In other embodiments, one, multiple or all functions of FIG. 12 can beimplemented by one, two or many MOS transistors. Also, one, multiple orall functions may be sub-divided in multiple blocks. Furthermore, two ormultiple functional blocks can be merged together for purposes ofimplementations.

FIG. 13A illustrates the concept of voltage translation and use ofvoltage translation for leakage reduction as per this invention. Asshown in FIG. 13A, a “voltage translator” 5161 is inserted in the signalpropagation path from one Logic function gate 5160 to another Logicfunction gate 5162. This voltage translator block will translate thevoltage on output signals 5156 driven by “standard logic function gate”5160 from “Vdd” to “Vddsp (“Vdd+Δv1”) and from “Vss” to “Vsssp”(“Vss−Δv2”) in addition to allowing the transition between Vddsp andVsssp. Hence the output signals of “Voltage translator” now transitionsbetween “Vddsp” (“Vdd+Δv1”) and “Vsssp” (“Vss−Δv2”). Output signals of“Voltage translator” are also the input signals to the next “Logicfunction gate” 5158. Hence, with the “Voltage translator” thus insertedbetween two “Logic function gates” the output signals of the driving“Logic function gate” would transition between “Vdd” and “Vss” but theinput signals of receiving “Logic function gate” would transitionbetween “Vddsp” (“Vdd+Δv1”) and “Vsssp” (“Vss−Δv2”). Such input signalsresult in “negative gate source voltage” if the transistors in “Logicfunction gate” were all connected to “Vdd” and “Vss”.

Embodiment with “Voltage translator” as shown in FIG. 13A will achieveleakage reduction at cost of more delay in the signal propagation path.While this could be an acceptable solution to some applications, it maypose unacceptable restriction for some other applications.

In another embodiment the “Voltage Translator” blocks are merged withthe “Logic function gate”. In this way “Logic function gates” have builtin “Voltage translator” functionality. This would allow voltagetranslation function to be merged with Logic computer and othernecessary logical and electrical functionality of a Boolean functiongate and achieve high speed along with the leakage reduction. FIG. 13Bshows signal flow between blocks that have CMOS Boolean gatefunctionality merged with Voltage translation functionality. As shownthe output signals and input signals transition between Vddsp and Vsssp.“Logic function gate with Voltage translation” 5170 and 5171 areconnected to all supply rails Vdd, Vddsp, Vss and Vsssp.

In other possible embodiments these can be connected to any 3 supplyrails if leakage reduction was desired only in PMOS or NMOS. Theinput/output signals in such case will transition between Vddsp and Vssor between Vdd and Vsssp depending on presence of the supply rails anddepending on the requirements.

FIG. 13A shows only a limited possible implementation of general schemeillustrated in FIG. 12. FIG. 12 illustrates general construction andconnectivity of a Logic function gate with reduced leakage technology ofthis invention.

For simplicity and consolidation of concepts the general constructiondiagram is illustrated with smaller number of sub-blocks in FIG. 14A.The “Logic computer” sub-block 5081, “Noise filter” sub-block 5087,“Input Receiver” sub-block 5084 and “Output Driver” sub-block 5083 ofFIG. 12 have been merged into a single sub-block in FIG. 14A. All othersub-blocks of FIG. 12 remain unchanged.

Thus any logic function gate in the Reduced Leakage CMOS Logic (RLCL)technology as per this invention may be represented by FIG. 14A. Asshown in FIG. 14A, each reduced leakage functional gate 5221 comprisesof four main functional units: a “Logic computer, Noise filter, Inputreceiver & output driver unit” 5220, a “Voltage translator unit” 5217, a“Current control Circuit” 5218 and a “Current control decision Circuit”5219. Each functional gate may have one or more inputs 5215 and one ormore outputs 5216 that may be connected to one or more or all of theseunits (5220, 5217, 5218, and 5219). One or more of these units (5220,5217, 5218, and 5219) may be connected to Supply1 (Vddsp) 5211, Supply2(Vdd) 5212, Supply3 (Vss) 5213, and Supply4 (Vsssp) 5214 as shown inFIG. 14A. One or more of these units can be merged together inimplementation or sub-divided further.

Multiple sub blocks of FIG. 14A can be merged together or eliminated asappropriate in various other embodiments of this invention. One,multiple or all functions of sub-blocks in FIG. 14A can be implementedone or many MOS transistors.

The fundamental design of the leakage reduction is embedded in eachBoolean logic function gate with reduced leakage such that whenconnected to other functional cells designed with same or compatibletechnology, MOS transistors with high leakage in the cell receivenegative gate-source voltage when they are not participating inoutput(s) transitions. This significantly reduces the leakage of HighSpeed (and high leakage) MOS transistors thereby drastically reducingthe leakage current in the entire cell. Each cell performs its ownleakage current reduction functions since all control and monitoringcontrol, functions and mechanisms are contained in the cell. Thistechnology may be known as “Reduced Leakage CMOS Logic” (“RLCL”)technology and circuits designed with RLCL technology may be known asRLCL circuits.

In practice, the voltage on Supply1 (Vddsp=Vdd+Δv1) will be higher thanthe voltage on Supply2 (Vdd) by a value Δv1 where Δv1 is determinedafter careful analysis of leakage, speed and other design considerationsby the implementation team at the time of IC implementation. In atypical modern semiconductor process Δv1 can be in range of 30millivolts to 200 millivolts (mv) (one millivolts is equal to 1/1000 ofone VOLT). In slightly older such as 65 Nano Meter (nm) CMOS processtechnology Δv1 is expected to be in range of 200 millivolts. Incurrently available leading edge 28 nm process technology Δv1 isexpected to be in range of 50 MILI VOLT to 100 MILI VOLT and in future20 nm process technology Δv1 is expected to be lower voltage. Similarly,the voltage on Supply3 (Vss) 5213 is higher than voltage on Supply4(Vsssp) by a value Δv2 where Δv2 is determined after careful analysis ofleakage, speed and other design considerations by the implementationteam at the time of IC implementation. Similar to Δv1, Δv2 can be inrange of 30 MILI VOLT to 200 MILI VOLT (mv) (one MILI VOLT is equal to1/1000 of one VOLT). In slightly older such as 65 Nano Meter (nm) CMOSprocess technology Δv1 is expected to be in range of 200 MILI VOLT. Incurrently available leading edge 28 nm process technology Δv1 isexpected to be in range of 50 MILI VOLT to 100 MILI VOLT and in future20 nm process technology Δv1 is expected to be lower voltage. Δv1 andΔv2 may or may not be equal and there is no pre-determined limitation onvalues of Δv1 and Δv2. This voltage relationship is true for allnotations where 4 supply rails (Supply1, Supply2, Supply3, Supply4,Vddsp, Vdd, Vss and Vsssp) are drawn or mentioned in this description ordiagrams. This voltage relationship is also true for embodiments whereonly 3 supply rails may be implemented. Values of Δv1 and Δv2 mentionedhere are only representative. Their range or values may be different ifthe IC implementation team would want to implement.

A family of logic function gates implemented with the RLCL technologymay be known as “Reduced Leakage CMOS Logic” or “RLCL” family of logicgates and a library of these gates may be known as RLCL library. As in astandard cell library of CMOS logic family, the standard Cell library inRLCL logic family consists of many cells with many and various Booleanfunctionality and drive strength with added advantage of substantiallyreduced leakage current. The mechanism to reduce leakage is containedwithin each basic cell. When implemented in an IC, RLCL logic gatesbehave and perform mostly in the same way as a normal CMOS Boolean logicgates that are already in use in the industry.

FIG. 14B, FIG. 14C and FIG. 14D show 3 different variations ofimplementation of reduced leakage current device of FIG. 14A. All ofthese implementations require 4 or 3 supply rails as described above. Inone possible embodiment as shown in FIG. 14B each of 4 functionality“Logic computer, Noise filter, input receiver and output drive”,“Voltage Translator”, “Current control circuit” and “current controldecision circuit” are comprised of both High Speed and Low Leakage CMOScomponents. In another embodiment as shown in FIG. 14C, each of threeblocks “Logic computer, Noise filter, input receiver and output drive”,“Voltage Translator” and “Current control circuit” are divided in twoseparate sections connected to each other and also connected to “currentcontrol decision circuit” wherein all circuit blocks in “Circuit section1” 25204 are comprised of “HIGH SPEED” CMOS components while all circuitblocks in “Circuit section 2” 25205 are comprised of LOW LEAKAGE CMOScomponents while “Current control decision circuit” 25206 are comprisedof LOW LEAKAGE CMOS components. In yet another embodiment, not shown inFigures, the “Current control decision circuit” 25206 of FIG. 14C isreplaced by a “Current control decision circuit comprised of both HIGHSPEED and LOW LEAKAGE CMOS components”. In yet another embodiment, notshown in Figures, the “Current control decision circuit” 25206 of FIG.14C is replaced by a “Current control decision circuit comprised of onlyHIGH SPEED and CMOS components”.

Yet another embodiment and variation of implementation of reducedleakage current device of FIG. 14A is represented in FIG. 14D where“Logic computer, Noise Filter, input receiver & Output driver”, ‘Currentcontrol circuit”, “Voltage translator”, and “‘Current control decisioncircuit” are merged together and are comprised of a mix and acombination of HIGH SPEED, LOW LEAKAGE and Uni Directional CMOScomponents.

As described earlier HIGH SPEED CMOS transistors can be large CMOStransistors of any type or low Vt, standard Vt, intrinsic CMOStransistors. Similarly a LOW LEAKAGE CMOS transistor can be a smalltransistor of any type or High Vt, High voltage (thick oxide) CMOStransistors. Uni-directional CMOS transistors are special CMOStransistors as proposed in this invention. A Unidirectional PMOStransistor “UP” conducts current only from first diffusion node tosecond but never conducts current from second diffusion node to first.

Similarly a unidirectional NMOS transistor “UN” also conducts currentonly from first diffusion node to second but never conducts current fromsecond diffusion node to first. Except for this nature ofuni-directional current flow “uni directional” CMOS transistors behavesimilar to standard CMOS transistors.

FIG. 15 illustrates a reduced leakage current inverter 5240 that has MOStransistors. Transistor symbols are defined here that apply to allrelevant symbols of MOS transistor relevant in this invention.

-   -   PMOS transistor Symbol with “HS” written under it means a HIGH        SPEED PMOS Transistor (PMOS-HS)    -   NMOS transistor symbol with “HS” written under it means a HIGH        SPEED NMOS Transistor (NMOS-HS)    -   PMOS transistor Symbol with “LL” written under it means a LOW        LEAKAGE PMOS Transistor (PMOS-LL)    -   NMOS transistor symbol with LL written under it means a LOW        LEAKAGE NMOS Transistor (NMOS-LL).    -   Any logic gate symbol with “HS” written in its body or under the        symbol means the LOGIC gate consisting of HIGH SPEED MOS        transistors.    -   Any logic gate symbol with “LL” written in its body or under the        symbol means the LOGIC gate consisting of LOW LEAKAGE MOS        transistors.

The PMOS-HS is a high speed (HS) PMOS transistor and NMOS-HS transistoris a high speed NMOS transistor. The PMOS-LL transistor is a Low LeakagePMOS transistor and NMOS-LL transistor is Low Leakage NMOS transistor.All modern semiconductor manufacturing houses (Semiconductor foundries)have these transistors as standard product offerings. Their use forvarious purposes is a standard practice in modern IC implementationsincluding in some of the typical circuits described earlier. Forexample, high Speed MOS (PMOS or NMOS) can be “Low Threshold” (Low Vt),Standard Voltage Threshold (Standard Vt) or Native MOS transistor.Similarly the low leakage transistor can be High Threshold (High Vt) orHigh Voltage or Thick Oxide or Double Oxide transistor. Many known andwell established manufacturing technologies are used to create HighSpeed and Low Leakage MOS transistors by Semiconductor foundries. As ageneral rule, a Low Leakage MOS transistor is a slow speed MOStransistor and conversely a High Speed MOS transistor is a High LeakageMOS transistor. Regardless of the manufacturing technologies used insemiconductor this leakage and speed relationship is true. Thisrelationship is driven by the very science (Physics) that govern allbehavior of MOS transistors and is a well known and practiced insemiconductor industry.

With reference to FIG. 15, inverter 5240 may have a PMOS-HS transistor(5241) and NMOS-HS transistor (5243) that are connected to each other(at their respective source and drains as shown) and to Supply2 (Vdd)line 5248 (the source of the PMOS transistor) and a Supply3 (Vss) line5249 (the source of the NMOS transistor), respectively. These two MOStransistor are also connected to an input port 5245 and an output port5246 of the inverter as shown in FIG. 15. This connection is similar toa classical CMOS inverter prevalent in Industry. The inverter of FIG. 15may also have a PMOS-LL transistor (5242) and NMOS-LL transistor (5244)that are connected to each other (at their respective source and drainsas shown), to the input port 5245 and to the output port 5246 as shown.Additionally, the PMOS-LL transistor and NMOS-LL transistor areconnected to a Supply1 (Vddsp) line 5247 and a Supply4 (Vsssp) line5250, respectively.

The PMOS-HS (5241) is a high speed (HS) PMOS transistor and NMOS-HStransistor (5243) is a high speed NMOS transistor. The PMOS-LLtransistor (5242) is Low Leakage PMOS transistor and NMOS-LL transistor(5244) is Low Leakage NMOS transistor.

In RLCL technology, the advantages of Low Leakage and High Speed MOStransistors are combined together along with the circuit designtechnology of connectivity to mitigate or eliminate the shortcomings ofspeed and leakage. In particular, when the Input Port (5245) is drivento Logic High (to a voltage of Vddsp, and not to Vdd as will be clearfrom following paragraphs), the High Speed NMOS transistor 5243 and LowLeakage NMOS transistor 5244 are turned ON. The High Speed (but alsohigh leakage) NMOS (5243) pulls down the output node 5246 with highspeed assisted by Low Leakage but slow NMOS transistor (5244). However,the High Leakage (High Speed) NMOS 5243 pulls the output node 5246 downonly to a voltage at Supply3 (Vss), but the Low Leakage NMOS transistor5244 pulls the output port 5246 down to Supply4 (Vsssp) which is at avoltage Δv2 lower than Vss.

Similarly when the Input Port 5245 is driven to Logic LOW (to voltage ofVsssp, and not to Vss, as will be clear from following paragraphs), theHigh Speed PMOS transistor 5241 and Low Leakage PMOS transistor 5242 areturned ON. The High Speed (but also High Leakage) PMOS (5241) pulls upthe output node 5246 with high speed, assisted by Low Leakage (but slow)PMOS transistor 5244. The High Speed (but also High Leakage) PMOS 5243pulls the output node UP only to voltage at Supply2 (Vdd), while the LowLeakage PMOS transistor 5242 pulls the output port 5246 up to Supply1(Vddsp) which is at a voltage Δv1 higher than Vdd. As clear from above,the output node thus swings from Vddsp to Vsssp and from Vsssp to Vddspbecause of this special circuit arrangement.

As in all CMOS ICs, the output of this functional gate (INVERTER in thisexample) is connected to inputs of other CMOS function gates so that theinputs of all logic function gates connected to the output of thisINVERTER will therefore transition from Vddsp to Vsssp and from Vsssp toVddsp. Since, the input of this inverter is also driven by output of asimilar CMOS gate with this exactly same voltage transition behavior,the input of this INVERTER will transition from Vddsp to Vsssp and fromVsssp to Vddsp.

As explained above, in operation, the input (5245) transitions betweenVddsp and Vsssp. In steady state (after completion of the transition),the Input port (5245) is held at Vddsp or Vsssp. When the Input is LOGICHIGH and at Vddsp, the gate-source voltage of High speed (and hence highleakage) PMOS transistor 5241 is negative because the source of thistransistor is connected to Vdd (Supply 2). The negative gate-sourcevoltage reduces the leakage current in this PMOS transistorsignificantly as per the leakage behavior explained earlier. TheGate-source Voltage of Low Leakage PMOS transistor 5242 is ZERO as inprevalent standard CMOS logic function gate. PMOS 5242 is a Low LeakagePMOS transistor by default and definition as provided by thesemiconductor foundry, hence the leakage current in this transistor isvery small by definition. Also, the PULL UP speed of this function gateis achieved by PULL UP current of PMOS 5241, therefore the size of LOWLeakage PMOS 5242 is small. Overall, because of small size and being aLOW LEAKAGE PMOS by definition, the leakage in PMOS 5242 is very small.

Similarly when the input port (5245) is LOGIC LOW and at Vsssp, thegate-source voltage of High speed (and hence high leakage) NMOStransistor 5243 is negative because the source of this transistor isconnected to a Vss (Supply 3) thus drastically reducing the leakagecurrent in this NMOS transistor. The Gate-source Voltage of Low LeakageNMOS transistor 5244 is ZERO as in prevalent standard CMOS logicfunction gate. But NMOS 5244 is a Low Leakage NMOS transistor by defaultand definition as provided by the semiconductor foundry, hence theleakage current in this transistor is very small. Also, the PULL DOWNspeed of this function gate is achieved by PULL DOWN current in NMOS5244, therefore the size of LOW Leakage NMOS 5244 is small. Overall,because of small size and being a LOW LEAKAGE NMOS by definition, theleakage in PMOS 5242 is very small.

In practice the size of Low Leakage PMOS 5242 and Low Leakage NMOS 5244transistors are chosen by various standard design considerations such asleakage current, noise margin and speed etc.

As can be understood from above explanation, in this mechanism, thefunction of leakage reduction is caused by the voltage translation ofthe output port (5246) signal which is input to other logic functiongates that results in negative voltage for the large and High Leakage(but high speed) MOS transistors (which are the main functional andspeed provider for the logic function gate) thereby reducing leakagecurrents in these main transistors. Additionally the Low Leakage PMOSand NMOS transistors 5242 and 5244 provide assistance to the High SpeedPMOS and NMOS transistors 5241 and 5243 respectively during outputtransitions. More importantly these LOW Leakage PMOS and NMOStransistors 5242 and 5244 pull the output node of the function gate toVddsp and Vsssp respectively. Also these Low Leakage PMOS and NMOStransistors 5242 and 5244 do not hinder the logic and voltage operationof the logic functional gate in any way.

The use of dual MOS transistors to mitigate each others disadvantages ina functional gate in such a way that the output (or input) voltages gettranslated automatically to provide negative gate-source voltage to theHigh Leakage MOS transistors in this same gate or in the gate(s) towhich the output is connected is one of the fundamental designprinciples for the leakage current reduction as per this invention.

The circuit presented in FIG. 15 has all 4 functions of FIG. 14A (5217,5218, 5219 and 5220) embedded in these 4 transistors (5241, 5242, 5243and 5244). The “Logic computer, Noise Filter, Input Receiver & OutputDriver” (5220) function is performed by all PMOS and NMOS transistorscombined. The “Voltage translator” function is performed by Low LeakagePMOS transistor 5242 and Low Leakage NMOS transistor 5244 along withtheir special connectivity to power supplies Vddsp and Vsssprespectively. The “Current control Circuit” 5218 function is performedby the special connectivity of High Speed PMOS and NMOS transistors 5241and 5243 to Supply2 (Vdd) and Supply3 (Vss) respectively and by LowLeakage PMOS and NMOS transistors 5242 and 5244. During outputtransition large switching current flows through High Speed PMOS andNMOS transistors 5241 and 5243. Then output voltage is driven to Vddspor Vsssp by Low Leakage PMOS and NMOS transistors 5242 and 5244respectively. After the transition in input is completed the leakagecurrent is controlled and significantly reduced in High Speed PMOS andNMOS transistors 5241 and 5343 due to negative gate-source voltage. Theleakage currents in “Low Leakage” PMOS and NMOS transistors 5242 and5244 are small by definition. It must be noted that the input voltageswing differential from Vdd and Vss is achieved by the voltagetranslation function in the logic cell that drives the input of thisLogic functions cell and has same or compatible voltage translationmechanism for its output port. The “Current control decision Circuit”5218 function is performed implicitly by the negative gate-sourcevoltage biasing provided by the way power supply, inputs and outputs oflogic cells are connected together.

Vddsp, Vdd, Vss and Vsssp are 4 separate power supply rails. These railsare generated for the whole IC or one or multiple blocks by one ormultiple voltage regulator or other supply generator(s) that is eitherembedded in the same IC chip or is externally located. Generator ICs ofsuch multiple supply rails are available as standard products insemiconductor industry. Multiple power supplies generated internally orexternally in any IC is standard practice in semiconductor design andusage industry. Many supply generator ICs are available as standardproducts that can fulfill the requirements. Intellectual Property (IP)blocks with this functionality are available to be embedded inside an ICthat can provide such power rails with or without minor modifications.

When the input port 5245 is at Logic HIGH (Vddsp), leakage currents inPMOS transistors 5241 and 5242 is significantly smaller than normal CMOSgate, but since both NMOS transistors 5243 and 5244 are ON, there is ashort circuit current between Supply 3 and Supply 4 (Vss and Vsssp)through NMOS transistors 5243 and 5244. Similarly, when the Input port5245 is at LOGIC LOW (Vsssp), the leakage currents in NMOS transistors5243 and 5244 are significantly smaller than normal CMOS gates but sincePMOS transistors 5241 and 5242 are both ON, there is a short circuitcurrent between supply rails Supply1(Vddsp) and Supply2 (Vdd). Thisembodiment is therefore buildable, but requires important chance in MOStransistor behavior through change in semiconductor process technologyto function. This new (to be designed) MOS transistor would need toconduct current only in one direction (from drain to source for NMOS andsource to drain for PMOS) and block current in other direction, in orderfor the INVERTER of FIG. 15 to function with substantially reducedLeakage Current but without short circuit current. Multiple viableprocess technologies may be used to design and manufacture such MOStransistors. But Development of such MOS transistor technology may taketime and effort by the semiconductor industry before it can becommercially available readily. Viable process change to implement suchspecial functionality transistors is detailed in later sections (FIGS.22-25).

Hence, this invention uses alternative methods and design to overcomethe current shortcomings of the circuit presented in FIG. 15, so thatRLCL technology can be used with currently available MOS transistors inpresently functioning semiconductor fabrication foundries. These methodshave been explained in following sections.

FIG. 16 illustrates alternative MOS transistor level implementation ofthe reduced leakage current inverter. As in case of the inverter of FIG.14A, in this embodiment also, there are four supply rails Supply1(Vddsp), Supply2 (Vdd), Supply3 (Vss) and Supply4 (Vsssp) 5285-5288.These supply rails are exactly same as in FIG. 15 with same voltage andfunctional relationships. In this embodiment the main inverter functionis performed by High Speed PMOS 5271 and High Speed NMOS 5272. As incase of the inverter of FIG. 15, an input port 5270 is driven by anotherRLCL circuit gate or compatible circuit component and transitionsbetween Vddsp and Vsssp. Port “out” 5280 is the output of this RLCLinverter. The RLCL inverter gate further consists of a CMOS inverter5291 that further consists of Low Leakage PMOS 5276 and Low Leakage NMOS5277. The RLCL inverter further consists of a second CMOS inverter 5292that further consists of Low Leakage PMOS 5278 and Low Leakage NMOS5279. The input of Inverter 5291 is connected to the output port 5280and its output 5281 is connected to the input of Inverter 5292 and tothe gate of Low Leakage PMOS transistor 5273 and to the gate of LowLeakage NMOS transistor 5275. The output 5282 of Inverter 5292 isconnected to the gates of High Speed PMOS 5274 and High speed NMOS 5276.The inverters 5291 and 5292 provide the functionality of “currentcontrol decision circuits” of FIG. 14A. The source node of High SpeedPMOS 5274 is connected to Supply2 (Vdd), and source node of Low LeakagePMOS 5273 is connected to Supply1 (Vddsp). The drain nodes of both ofthese PMOS transistors 5273 and 5274 are connected together and also tothe source node of High Speed PMOS 5271. Similarly the sources of Highspeed NMOS 5276 and Low Leakage NMOS 5275 are connected to Supply3 (Vss)and Supply4 (Vsssp) respectively. The drain nodes of the two NMOStransistors 5275 and 5276 are connected together and also to the sourcenode of High Speed NMOS transistor 5272. The drain nodes of High speedPMOS transistor 5271 and High Speed NMOS transistor 5272 are connectedtogether and also to the output port 5280. The output port 5280 is theoutput of this INVERTER and the Input port 5270 is the input of thisinverter.

Comparing RLCL INVERTER in FIG. 16 to the RLCL INVERTER in FIG. 15, itcan be seen that Low Leakage PMOS 5273 of FIG. 16 is equivalent to LowLeakage PMOS 5242 of FIG. 15. Similarly Low Leakage NMOS 5275 in FIG. 16is equivalent to the Low Leakage NMOS 5244 of FIG. 15. High Speed PMOStransistor 5271 of FIG. 16 is equivalent to High speed PMOS transistor5241 of FIG. 15 and High Speed NMOS transistor 5272 of FIG. 16 isequivalent to High Speed NMOS transistor 5243 of FIG. 15. High speedPMOS and NMOS transistors 5274 and 5276 have been added to eliminate orreduce the short circuit current of the embodiment of RLCL INVERTERshown in FIG. 15. Inverters 5291 and 5292 provide the necessary sensingand control functionality for eliminating or reducing this short circuitcurrent.

Even though, in the schematic in FIG. 16, the new RLCL INVERTER looksmuch larger and elaborate in size, the actual implementation is verycomparable to the INVERTER in FIG. 15 because the sizes of all LowLeakage MOS transistors are very small. In an actual layoutimplementation, these small transistors are located in auxiliary cellareas that would otherwise have been wasted in a normal CMOS INVERTERimplementation. Therefore the layout areas of RLCL function gates inRLCL library are comparable to the layout areas of equivalent NORMALCMOS gate in a NORMAL CMOS library. After implementation the overallsize of CMOS IC is NOT impacted significantly even with this transistorlevel complexity of an RLCL function gate. The INVERTER of FIG. 16represents the most basic but complete, fully functional and selfsufficient cell of the RLCL technology, RLCL circuit and RLCL library.

As in case of a NORMAL CMOS functional gate, only supply ports, inputports and output port(s) are visible and used by tools for chipimplementation. Complex connectivity within the function gate is neithervisible not used during chip (IC) implementation in RLCL technology aswell as standard CMOS technology. This means RLCL logic gates arecomparable to standard CMOS in ease of use in an IC.

With reference to FIG. 16, Input port 5270 transitions from Vddsp toVsssp and from Vsssp to Vddsp and is driven by another RLCL circuit orRLCL compatible circuit component. This is exactly same as described forthe inverter in FIG. 15.

When input port is LOGIC HIGH at voltage Vddsp, the Output port 5280 isdriven to LOGIC LOW. The output of inverter 5291 (node 5281) is at LOGICHIGH at voltage Vddsp and output 5282 of INVERTER 5292 is LOGIC LOW atvoltage Vsssp. A LOGIC HIGH (Vddsp) at node 5281 causes the Low LeakageNMOS 5275 to be ON. The output port 5280 is thus discharged to thevoltage of Vsssp through ON NMOS transistors 5272 and 5275. Thus LOGICLOW voltage at output port 5280 is deterministically at voltage ofVsssp. A LOGIC LOW (Vsssp) at node 5282 causes High Speed NMOS 5276 tobe OFF with its gate node driven to Vsssp. In this condition Low LeakagePMOS transistor 5273 is OFF since its gate node is driven by node 5281(which is at voltage Vddsp). The High Speed PMOS transistor 5274 is ONsince its gate node is driven by node 5282 (which is at Vsssp). Thiscauses the voltage on node 5294 to be Vdd (not Vddsp) which is also thesource node for High Speed PMOS transistor 5271. Since the INPUT port isLOGIC HIGH at voltage Vddsp, the PMOS transistor 5271 has its gate nodeat higher voltage than the source voltage. This is a negativegate-source voltage for High Speed PMOS 5271, which not only causes thepull up path from output port 5280 to be cut off from supply lines Vddspand Vdd but also significantly reduces the leakage in High Speed PMOS5271. In this way the RLCL inverter of FIG. 16 has its pull down pathdeterministically driven to be Vsssp and significantly small leakagecurrent in PULL UP path.

However, there is a secondary effect of this method and connectivitywhich is important to understand and analyze. In this condition (wheninput is at LOGIC HIGH at Vddsp, output port is driven to Vsssp, node5281 is at Vddsp, and node 5282 is Vsssp), when the output port 5280 isdriven to Vsssp, the middle node 5293 is also driven to Vsssp through ONNMOS transistor 5272. This node then becomes the source node for HIGHSpeed NMOS 5276. The gate node of High Speed NMOS 5276 is also at Vsssp.Other diffusion terminal of this High Speed NMOS 5276 that is connectedto Vss now becomes the drain node of High Speed NMOS transistor 5276because it is at higher voltage than node 5293. Thus High Speed NMOS5276 has ZERO gate-source voltage and not a negative gate-sourcevoltage. Therefore, potentially it may have leakage current (since it isa high leakage MOS transistor). But the High Speed NMOS 5276 doesn'thave high leakage current. Since the source node of High Speed NMOS 5276is at voltage Vsssp and the drain node is at voltage Vss, the voltagedifferential between drain and source terminals is only Δv2. In practicethis differential voltage (Δv2) is an order of magnitude smaller thanthe normal voltage on Vdd, the drain source voltage of this High SpeedOFF NMOS (5276) is an order of magnitude lower than the OFF MOStransistor in a normal CMOS logic circuit. According to the leakageproperty of MOS transistors where the leakage current is proportional tothe drain-source voltage, because of this very small source-drainvoltage the Leakage current of this OFF NMOS 5276 is substantiallysmaller than an OFF NMOS of a normal CMOS function gate.

Thus when input port 5270 is LOGIC HIGH at voltage Vddsp, due tonegative gate-source voltage in High Speed PMOS 5271, and very smalldrain-source voltage of High Speed NMOS 5276, RLCL inverter of FIG. 16has substantially reduced leakage current as compared to a NORMAL CMOScircuit in this steady state. Also it has substantially small shortcircuit current unlike the RLCL inverter of FIG. 15.

All other OFF MOS transistors are LOW LEAKAGE and small MOS transistorsin size and hence they have substantially low leakage currents bydefinition.

Similarly, when input port is LOGIC LOW at voltage Vsssp, the Outputport 5280 is driven to LOGIC HIGH at voltage Vddsp. The output ofinverter 5291 (node 5281) is at LOGIC LOW at voltage Vsssp and output5282 of INVERTER 5292 is LOGIC HIGH at voltage Vddsp. A LOGIC LOW(Vsssp) at node 5281 causes the Low Leakage PMOS 5273 to be ON. Theoutput port 5280 is thus charged to Vddsp through ON PMOS transistors5271 and 5273. Thus LOGIC HIGH voltage at output port 5280 isdeterministically at voltage of Vddsp. A LOGIC HIGH (Vddsp) at node 5282causes High Speed PMOS 5274 to be OFF with its gate node driven toVddsp. In this condition Low Leakage NMOS transistor 5275 is OFF sinceits gate node is driven by node 5281 (which is at voltage Vsssp). TheHigh Speed NMOS transistor 5276 is ON since its gate node is driven bynode 5282 (which is at Vddsp). This causes the voltage on node 5293 tobe Vss (not Vsssp) which is also the source node for High Speed NMOStransistor 5272. Since the INPUT port is LOGIC LOW at voltage Vsssp, theNMOS transistor 5272 has its gate node at lower voltage than the sourcevoltage (which is Vss). This is a negative gate-source voltage for HighSpeed NMOS 5272, which not only causes the pull down path from outputport 5280 to be cut off from supply lines Vsssp and Vss but alsosignificantly reduces the leakage in High Speed NMOS 5272. In this waythe RLCL inverter of FIG. 16 has its pull up path deterministicallydriven to be Vddsp and significantly small leakage current in PULL DOWNpath.

Similar to the case when INPUT port 5270 was at LOGIC HIGH (Vddsp),there is a secondary effect of leakage in this method and connectivity.In this condition (input is at LOGIC LOW at Vsssp, output port is drivento Vddsp, node 5281 is at Vsssp, and node 5282 is Vddsp), when theoutput port 5280 is driven to Vddsp, the middle node 5294 is also drivento Vddsp through ON PMOS transistor 5271. This node then becomes thesource node for HIGH Speed PMOS 5274. The gate node of High Speed PMOS5274 is also at Vddsp. Other diffusion terminal which now drain of HighSpeed PMOS transistor 5274 is now connected to Vdd. Thus High Speed PMOS5274 has ZERO gate-source voltage (not a negative gate-source voltage).Therefore, potentially it may have leakage current (since it is a highleakage MOS transistor). But the High Speed PMOS 5274 doesn't have highleakage current. Since the source node of High Speed PMOS 5274 is atvoltage Vddsp and the drain node is at voltage Vdd, the voltagedifferential between drain and source terminals is only Δv1. In practicethis differential voltage (Δv1) is almost an order of magnitude smallerthan the normal voltage differential of Vdd. Thus the drain sourcevoltage of this High Speed OFF PMOS (5274) is an order of magnitudesmaller than the OFF MOS transistor in a normal CMOS logic circuit.According to the leakage property of MOS transistors where the leakagecurrent is proportional to the drain-source voltage, because of thisvery small source-drain voltage the Leakage current of this OFF PMOS5274 is substantially smaller than an OFF NMOS of a normal CMOS functiongate.

Thus when input port 5270 is LOGIC LOW at voltage Vsssp, due to negativegate-source voltage in High Speed NMOS 5272, and very small drain-sourcevoltage of High Speed PMOS 5274, RLCL inverter of FIG. 16 hassubstantially smaller leakage current as compared to a normal CMOScircuit in this steady state. Also it has substantially smaller shortcircuit current unlike the RLCL inverter of FIG. 15.

All other OFF MOS transistors are LOW LEAKAGE and small MOS transistorsand hence they have substantially low leakage currents by definition.

During transition, the INVERTER of FIG. 16 behaves differently.

While in steady state, Low Leakage MOS transistors provide deterministiclogic state to the output port in response to the input logic state, andalso a mechanism for reduce leakage, these two behaviors alone are notsufficient for this inverter to be used commercially. A logic functiongate needs to compute fast and transition its output quickly in responseto appropriate change(s) in the inputs. High Speed of transition ofoutput port when required is a critical and important requirement inpractical ICs.

In RLCL technology the transition speed performance is provided by HighSpeed MOS transistors but the leakage in high speed transistors isreduced substantially by use of active designs and methods

High speed operation of RLCL inverter is explained again with FIG. 16.

When Input port 5270 is at LOGIC LOW (at voltage Vsssp), the output port5280 is charged to Vddsp through ON PMOS transistors 5273 and 5271. TheHigh Speed NMOS transistor 5276 is ON. Node 5293 is discharged to Vss.The HIGH Speed NMOS transistor 5272 is OFF. In this state this inverteris ready for a transition in the output whenever input changes. Thissteady state can be present for long time but the inverter hassubstantially reduced leakage current in this steady state as explainedearlier. It must be noticed that again that node 5293 is at Vss in thisstate.

When the INPUT transitions from LOGIC LOW (Vsssp) to LOGIC HIGH (Vddsp),High Speed NMOS transistor 5272 turns ON (from OFF) and High speed PMOStransistor (5271) turns OFF (from ON). Since node 5293 was alreadydischarged to Vss, the output port 5280 starts discharging to Vss byPULL DOWN current through High Speed NMOS transistors 5272 and 5276 assoon as input transitions HIGH. High Speed PMOS 5271 turns OFF as HighSpeed NMOS 5272 turns ON. OFF PMOS transistor 5271 cuts OFF the pull upcurrent path of output port. The output port discharge continues throughHigh Speed NMOS transistors 5272 and 5276. Once the output port 5280crosses the LOGIC THRESHOLD level of inverter 5291 (which isapproximately half way between Vddsp and Vsssp because of normalfunctional nature of a CMOS gate), the output of this INVERTER (5291)transitions from LOGIC LOW to LOGIC HIGH (Vsssp to Vddsp). This switchesON the Low Leakage NMOS 5275 which provides the PULL DOWN current pathto Vsssp. Logic Transition at node 5281 causes the logic transition inthe output of inverter 5292 from LOGIC HIGH to LOGIC LOW (at Vsssp).This causes the High Speed NMOS 5276 to turn OFF thus eliminating theshort between Vss and Vsssp. By the time High Speed NMOS transistor 5276turns OFF the output port has already made transition to LOGIC LOW. Thisbehavior is guaranteed because the event of switching OFF of High SpeedNMOS 5276 starts only after the output port 5280 has alreadytransitioned to LOGIC LOW. Also there is ample time difference betweenthe events of output port 5280 making transition to LOGIC LOW and HighSpeed NMOS transistor 5276 switching OFF. In effect, the speed oftransition to LOGIC LOW at output port of this gate is caused by PULLDOWN current through high Speed NMOS transistors 5272 and 5276. AfterHigh Speed NMOS transistor 5276 is turned OFF, the discharge currentthrough Low Leakage NMOS transistor 5275 and High Speed NMOS transistor5272 discharges output port 5280 to lower voltage Vsssp and keeps itthere in steady state till the input(s) change again to cause the outputtransition in opposite direction.

This steady state is already described in paragraphs above where thelogic gate waits for transition again, with substantially reducedleakage and substantially small short circuit current.

Similarly the transition of input port 5270 from LOGIC HIGH to LOGIC LOW(from Vddsp to Vsssp) causes PULL UP current from Vdd to output port5280 through High Speed PMOS transistors 5274 and 5271 providing fasttransition time. Then the output port 5280 is pull up to Vddsp throughLow Leakage PMOS transistor 5273 and High Speed PMOS transistor 5271 forholding a LOGIC HIGH at output port 5280 in steady state at Vddsp asexplained below.

When Input port 5270 is at LOGIC HIGH (at voltage Vddsp) in steadystate, the output port is discharged to Vsssp through ON NMOStransistors 5272 and 5275. The High Speed PMOS transistor 5274 is ONcharging the node 5294 to Vdd.

Now the INPUT 5270 transitions from LOGIC HIGH (Vddsp) to LOGIC LOW(Vsssp), High Speed PMOS transistor 5271 turns ON (from OFF) and Highspeed NMOS transistor (5272) turns OFF (from ON). Since node 5294 wasalready charged to Vdd, the output port 5280 starts charging to Vdd byPULL UP current through High Speed PMOS transistors 5271 and 5274 assoon as input transitions LOW. High Speed NMOS 5272 turns OFF as HighSpeed PMOS 5271 turns ON. The NMOS transistor 5271 that is turning OFFcuts OFF the pull down current path of output port 5280. The output portcharging continues through High Speed PMOS transistors 5271 and 5274.Once the output port crosses the LOGIC THRESHOLD level of inverter 5291(which is approximately half way between Vddsp and Vsssp because ofnormal functional nature of a CMOS INVERTER), the output of thisINVERTER (5291) transitions from LOGIC HIGH to LOGIC LOW (Vddsp toVsssp). This switches ON the Low Leakage PMOS 5273 which provides thePULL UP current path to Vddsp. This Logic transition at node 5281 causesthe logic transition on the output of inverter 5292 from LOGIC LOW toLOGIC HIGH, pulling the node 5282 up to Vddsp. LOGIC HIGH (Vddsp) atnode 5282 turns OFF PMOS 5274 thus eliminating the short between Vdd andVddsp. By the time High Speed PMOS transistor 5274 turns OFF the outputport has already made transition to LOGIC HIGH. This behavior isguaranteed because the event of switching OFF of High Speed PMOS 5274starts only after the output port 5280 has already crossed the thresholdof the transition to LOGIC HIGH. Again, there is ample time differencebetween the events of output port 5280 making transition to LOGIC HIGHand High Speed PMOS transistor 5274 switching OFF. In effect thetransition to LOGIC HIGH at output port 5280 is caused by PULL UPcurrents through high Speed PMOS transistors 5271 and 5274. Once theHigh Speed PMOS transistor 5274 is OFF, the pull up current through PMOStransistors 5271 and 5273 charges the output port 5280 to higher voltageVddsp and keeps it there in steady state till the input(s) change againto cause an output transition in opposite direction.

This steady state is also already described in above paragraphs.

An RLCL logic gate thus uses high speed MOS transistors to achieve highspeed performance, low leakage MOS transistors to maintain voltage atthe output port, voltage translation of the output port through itsconnectivity and design, low leakage MOS transistors to recognizetransition behavior and provide necessary control signals to variousportions of design that help logic transition and leakage reduction anddeterministic voltage supply rails along with active circuit designmethods and connections to achieve leakage reduction through negativegate-source voltage and substantially reduced source drain voltage intransistors that have tendency of high leakage current in a standardCMOS design. Additionally all these features and functionalities arecontained within a basic cell in this technology. These basic individualcells are fully compatible with each other with the same simplicity andease as that of a normal CMOS circuit cells (or logic gates) currentlyused in semiconductor industry.

A designer has the freedom to adjust voltage differences between Vdd andVddsp and Vss and Vsssp (Δv1 and Δv2), choice of MOS transistor for LowLeakage and High Speed MOS devices to adjust and achieve desired speed,leakage, area and power of the IC. These choices are similar to thechoices that an engineer needs to make in using a non-RLCL (or normalCMOS) circuit gates. As described above, Δv1 and Δv2 can be in range of20 mili Volts (mV) to 200 mili Volt (mv) or little more depending on thefabrication process node chosen for the IC being implemented. High SpeedNMOS and PMOS transistor sizes will be chosen according to the requireddrive strength and speed as is commonly done in a normal CMOS circuitdesign. Sizes of Low Leakage MOS transistors are expected to be minimumallowed by the process geometry or slightly higher to eliminate anycoupling noise issues. However, for various leakage and speed tradeoffthe ratio of sizes of different transistors can be varied, using normalengineering expertise, common in semiconductor industry.

The methods used for choosing sizes and voltage used in RLCL technologyare not unusual. They are same as the ones currently used by peopleadept in the art of CMOS circuit design.

The general construction of RLCL circuits that use output port togenerate various control signals can be divided in standard sub-blocksor sections of functionality as shown in FIG. 16. Basic constructionblocks as shown in FIG. 14A can be recognized in the transistor levelimplementation of the INVERTER of FIG. 16. For example, in FIG. 16,blocks 5295 and block 5296 and components inside these blocks togethercorrespond to “Current Control Circuit” 5218 of FIG. 14A. Similarlyblock 5298 from FIG. 16 and components within this block correspond to“Current control decision circuit” (5219) of FIG. 14A. Blocks 5297, 5296and 5295 of FIG. 16 and components within these blocks togethercorrespond to “Logic Computer, Noise Filter, Input receiver and outputdriver” 5220 of FIG. 14A. Part of blocks 5295 and 5296 in FIG. 16 alongwith components from block 5298 correspond to “voltage translator” 5217of FIG. 14A.

FIG. 17 illustrates a block diagram level implementation of the circuitin FIG. 14A and general construction of one embodiment of RLCL functiongates. As shown in FIG. 17, the “current control decision circuit” 5415is connected to the output port 5241 of the logic function gate. Anybasic functional gates in RLCL technology (or RLCL circuit blocks) haveone output port and one or many Input ports as shown in FIG. 17. Anyfunctional gate with more than one output ports are constructed bycombining two or more basic logic gates. This same property exists in astandard and normal CMOS circuit gates currently used in industry.

FIG. 17 represents a general and expanded block level construction of alogic gate using RLCL technology where “current control decisioncircuit” uses output port of the functional gate for its recognition,monitoring and control functionalities.

Other type of RLCL circuits are ones that do not use output port togenerate control signals for monitoring and controlling switching andleakage behavior of the circuit. These are discussed later.

As shown in FIG. 17, “Logic Computer, Noise Filter, Input receiver andoutput driver” block 5220 of FIG. 14A is divided in two parts “Pull uplogic computation circuit” 5412 and “Pull down logic computationcircuit” 5413. Similarly, the “current control” block 5218 of FIG. 14Ais divided into two separate blocks “Pull up current control circuit”5411, and “Pull down current control circuit” 5414. Input ports 5420 areone or multiple input ports connected to “Pull UP Logic ComputationCircuit” (5412) and “Pull down computation circuit (5413)”. In Additionto inputs 5420, “Pull up logic computation circuit” 5412 is connected to“Pull up current control Circuit” 5411, output port 5421 and “Pull downlogic computation Circuit” 5413. Similarly, “Pull down logic computationcircuit” 5413 is connected to input(s) 5420, “Pull Down current controlCircuit” 5414, output port 5421 and “Pull up logic computation Circuit”5412. The “Pull up current control circuit” 5411 is connected to Supplyrails “Supply1” (Vddsp) 5416 and Supply2 (Vdd) 5417 and to the “Currentcontrol decision circuit” 5415 and “Pull up logic computation circuit”5412. “Pull down current control circuit” 5414 is connected to Supplyrails “Supply3” (Vss) 5418 and Supply4 (Vsssp) 5419 and to the “Currentcontrol decision circuit” 5415 and “Pull down logic computation circuit”5413. The “Current Control Decision Circuit” 5415 is connected to “Pullup current control circuit” 5411, “Pull Down current control circuit”5414, output port 5421 and power supply rails Supply1 5416, Supply25417, Supply3 5418 and Supply4 5419. Any of the functional blocks 5411,5412, 5413, 5414 and 5415 may be connected to all Supply rails Supply15416, Supply2 5417, Supply3 5418, Supply4 5419 or any one or multiple ofthem.

FIG. 17 represents a block level construction of any RLCL logic functiongate. As already described in paragraphs above, FIG. 16 is transistorlevel implementation of the simplest RLCL logic function gate—anINVERTER according to the circuit scheme presented in more abstract formin FIG. 17. “Pull up logic computation circuit” 5412 of FIG. 17 isrepresented by a single PMOS transistor 5271 in FIG. 16. The “Pull downlogic computation circuit” 5413 of FIG. 17 is represented by a singleNMOS transistor 5272 in FIG. 16. “Pull Down current control circuit”5414 in FIG. 17 is represented by block 5295 in FIG. 16. The “Pull upcurrent control circuit” 5411 of FIG. 17 is represented by block 5296 inFIG. 16. “Current control decision circuit” 5415 of FIG. 17 isrepresented by block 5298 in FIG. 16.

More complex logic function gates are also constructed using the schemepresented in FIG. 17 making small modification without deviating fromthe main principles and working of circuit presented in FIG. 17.

FIG. 18 shows transistor level implementation of a NAND2 function gatewith RLCL technology using the general scheme shown in FIG. 17. NAND2 isa 2 input NAND function defined in a NORMAL BOOLEAN Logic Function suchthat its it has two LOGIC INPUTS and its output is at LOGIC LOW onlywhen both inputs are at LOGIC HIGH. Otherwise output is at LOGIC HIGH inall other conditions and combination of INPUT states. In comparing FIG.18 with FIG. 16, “Pull up current control circuit” 5501, “Pull downcurrent control circuit” 5504 and “current control decision circuit”5505 in FIG. 18 are same as in RLCL INVERTER of FIG. 16. However, the“Pull up logic computation circuit” 5502 and “Pull down logiccomputation circuit” 5503 are different from the RLCL INVERTER shown inFIG. 16, because of change in functionality. As in case of INVERTER inFIG. 16, high speed logic transition on output 5510 of the NAND2 in FIG.18 is facilitated by current through High Speed MOS transistors andoutput is held at steady state at Vddsp or Vsssp by Low Leakage MOStransistors.

As mentioned above, the NAND2 is a 2 input Boolean NAND function whereNAND is “NOT OF AND” defined by a Boolean binary function such that theoutput is at LOGIC LOW only when both INPUT ports are at LOGIC HIGH. Inall other combinations of input (such as INPUT_1 (In_1) at LOGIC HIGHand INPUT_2 (In_2) at LOGIC LOW or INPUT_1 (In_1) at LOGIC LOW andINPUT_2 (In_2) at LOGIC HIGH or INPUT_1 (In_1) and INPUT_2 (In_2) bothat LOGIC LOW) the output is at LOGIC HIGH.

Various currents and voltages in this NAND2 function gate behave insimilar ways as in the INVERTER of FIG. 16. As in case of the RLCLINVERTER of FIG. 16, the input ports of RLCL NAND2 function gate asshown in FIG. 18 also transition between Vddsp and Vsssp. In one steadystate condition, when both the inputs In_1 and In_2 (5511) are LOGICHIGH at Vddsp, High Speed PMOS transistors 5523 and 5524 are OFF whileHigh Speed NMOS transistors 5525 and 5526 are ON. Output port “out” 5510is at LOGIC LOW. Since node 5510 is input to the Low Leakage inverter5551 consisting of Low Leakage PMOS and NMOS transistors 5529 and 5530,its out output node 5541 is LOGIC HIGH at Vddsp. Node 5541 is also theinput for Low Leakage inverter 5552 consisting of Low Leakage PMOS andNMOS transistors 5531 and 5532 respectively, the output of this inverternode 5542 is LOGIC LOW at Vsssp. As shown in FIG. 18, node 5541 drivesthe gate nodes of Low Leakage PMOS 5521 and Low Leakage NMOS 5527. Node5542 drives gate nodes of High Speed PMOS 5522 and High Speed NMOS 5528.In this steady state because node 5541 is at LOGIC HIGH (Vddsp) and node5542 is at LOGIC LOW (Vsssp), Low Leakage NMOS 5527 is ON while HighSpeed NMOS 5528 is OFF. Output port 5510 is therefore discharged toVsssp through ON NMOS transistors 5525, 5526 and 5527 in series. It canbe understood by people adept in the ART of CMOS circuit design thatthere is no other possible state of output port 5510 than to be atVoltage Vsssp in steady state when inputs In_1 and In_2 both are atLOGIC HIGH at Vddsp.

In this state the High Speed PMOS transistor 5522 is ON and Low LeakagePMOS transistor 5521 is OFF. Because of this, the middle node 5561 ischarged to Vdd (not Vddsp). Node 5561 is also the source node for Highspeed PMOS transistors 5523 and 5524. The gate nodes of High Speed PMOStransistors 5524 and 5523 are at Vddsp since they are connected to inputports In_1 and In_2. Thus these two high speed PMOS transistors 5524 and5523 have negative gate source voltage which means they havesubstantially reduced leakage current when they are OFF in this steadystate. ON High Speed PMOS transistor 5522 in this state also means thatthis gate is ready for an output transition to LOGIC HIGH quicklywhenever appropriate input transitions occur.

In this steady state the short circuit current control between LowLeakage NMOS transistor 5527 and High Speed NMOS transistor 5528 happenin exactly same way as the RLCL invert of FIG. 16. Since Low LeakageNMOS 5527 is ON because its gate is driven to Vddsp by node 5541, middlenode 5562 is pulled down to Vsssp. This means node 5562 serves as asource node for High Speed NMOS 5528. The gate of this High Speed NMOS5528 is at Vsssp as driven by node 5542. Thus this High Speed NMOS 5528has ZERO (not negative) gate-source voltage. However, the voltagedifference between drain and source of this High Speed NMOS 5528 is onlyΔv2 which in practice is an order of magnitude smaller than Vdd.Therefore the source-drain voltage of this OFF High Speed NMOS is verysmall which results in significantly lower leakage current as explainedin the property of MOS transistor and hence significantly smaller shortcircuit current between Vss and Vsssp.

If any or both of the input ports 5511 (In_1 or In_2) transition toLOGIC Low at voltage Vsssp, the PULL UP current path from Vdd or Vddspto output port 5510 starts conducting current while the PULL DOWN pathfrom output port 5510 to Vss or Vsssp is cut off. Thus in steady statewhen one or both of the input ports In_1 or In_2 are at Logic Low, theoutput port 5510 is at Logic HIGH. In this case output of inverter 5551is LOGIC LOW at Vsssp and output of inverter 5552 is LOGIC HIGH atVddsp. This will cause Low Leakage PMOS 5521 to be ON and High SpeedPMOS transistor 5522 to be OFF. Output port 5510 is therefore charged toVddsp through PULL up current through ON Low Leakage PMOS 5521 and oneor both of the ON High Speed PMOS transistors 5523 and 5524. The Pulldown path from output to Vss/Vsssp is cut OFF because one or both of theNMOS transistors 5525 and 5526 are OFF. In this state, high speed NMOS5528 is ON and Low Leakage NMOS 5527 is OFF. Thus the internal node 5562that is also the source node for High Speed NMOS 5526 is at Voltage Vss(not Vsssp). This means one or both of High Speed NMOS transistors 5525and 5526 have negative gate—source voltage because the gate node isdriven by input ports to Vsssp. Thus the PULL DOWN path in this statehas significantly reduced leakage current. Again by similar phenomenonas described for RLCL inverter of FIG. 16, the short circuit currentbetween Low Leakage PMOS transistor 5521 and High Speed PMOS transistor5522 is very small because the OFF High Speed PMOS transistor 5522 hasZERO gate-source voltage but only a very small Δv1 source-drain voltageacross the High Speed PMOS 5522.

Overall in both steady state conditions (output port 5510 is HIGH orLOW) the leakage current NAND2 RLCL gate is significantly small ascompared to a normal CMOS NAND2 gate.

As in case of RLCL INVERTER of FIG. 16, during output transition thebehavior of transistors is different. Assume that the NAND2 RLCL gate isin one steady state where both inputs are LOGIC HIGH and output is LOGICLOW. In this state, the High Speed PMOS transistors 5523 and 5524 areOFF and High Speed PMOS transistor 5522 is ON. High Speed NMOStransistor 5528 is OFF and Low Leakage NMOS transistor 5527 is ON. Fromthis state if one or both of the inputs transition to LOGIC LOW toVsssp, the PULL UP current path through High Speed PMOS 5523 and/or 5524starts turning ON. High Speed PMOS 5522 was ON already. As the PULL UPpath turns ON because of turning ON of High Speed PMOS 5523 and/or 5524,the Pull down current Path starts turning OFF because High Speed NMOStransistors 5525 and/or 5526 start turning OFF. When the output port5510 crosses the inverter Logic Low voltage threshold inverter 5551output node 5541 transitions to LOGIC LOW and output node 5542 ofinverter 5552 transitions to logic HIGH. Transitions of these two nodescause Low Leakage PMOS 5521 to turn ON and High Speed PMOS 5522 to turnOFF. This pulls the output port 5510 and middle node 5561 to Vddsp. TheHigh Speed PMOS transistor 5522 turns OFF but only after the LOGICtransition of output node 5510 is completed because only after the LOGICtransition of output port 5510, nodes 5541 and 5542 make the LOGICtransitions. This way the output node 5510 transitions from LOGIC LOW toLOGIC HIGH through High Speed PMOS transistors path 5522 and 5523 and/or5524 but in steady state is held at LOGIC HIGH at voltage Vddsp by theLow Leakage Pull UP path consisting of Low Leakage transistor 5521 inseries with High Speed PMOS transistors 5523 and 5524. High Speed PMOStransistors cause high speed transition to the output port whenappropriate.

Similarly when the output port 5510 is in steady state at LOGIC HIGHbecause one or both of the input ports are at LOGIC LOW, node 5541 isLOGIC LOW at Vsssp and node 5542 is LOGIC HIGH at Vddsp. In this stateHigh Speed NMOS transistor 5528 is ON, Low Leakage NMOS transistor 5527is OFF. Similarly, the Low Leakage PMOS transistor 5521 is ON and HighSpeed PMOS transistor 5522 is OFF. When one or both of the input portsIn_1 and In_2 transition such that both the inputs are now at LOGIC HIGHat Vddsp, the PULL DOWN current path from output port 5510 to Vss turnsON through ON High Speed NMOS transistors 5525, 5526 and 5528, while thePULL up current path turns OFF because both High Speed PMOS transistors5523 and 5524 turn OFF. Output port thus discharges quickly to Vss withPULL down current path consisting of High Speed NMOS transistors 5525,5526 and 5528. Hence the transition is fast. Again, when output port5510 crosses threshold voltage of inverter 5551 node 5541 transitions toLOGIC HIGH at Vddsp and node 5542 transitions to LOGIC LOW at Vsssp.This turns ON Low Leakage NMOS transistor 5527 and turns OFF High SpeedNMOS transistor 5528. But before High Speed NMOS 5528 turns OFF, theoutput node has already made a transition to LOGIC LOW because onlyafter this transition, nodes 5541 and 5542 have made transitions totheir opposite LOGIC states. Low Leakage NMOS 5527 pulls the output nodeDOWN to Vsssp.

As obvious from above explanation, the RLCL NAND2 function gate

-   -   Performs the Boolean Binary LOGIC function as required by        definition of a NAND2 functional gate    -   Input and output ports behave in the same way as a normal CMOS        NAND2 gate    -   Achieves fast transition by use of High Speed CMOS transistors.        This is a desired requirement of modern ICs in the industry    -   Achieves significantly smaller leakage current than the normal        CMOS Logic circuits by use of negative gate-source voltage to        High Speed CMOS transistors in steady state (but not hindering        their operation during transition)        The circuits shown in FIG. 16 and FIG. 18 are two basic examples        of RLCL logic function gates. They represent construction and        functioning of all basic cells that can constitute the library        of RLCL logic function gates. By replacing the High Speed PMOS        and NMOS devices in “Pull up logic computation Circuit” and        “Pull Down logic computation Circuit” in both FIG. 16 and FIG.        18, any Boolean Function equivalent to a normal CMOS Logic gate,        can be constructed. More complex Logic function cells with more        than one output in RLCL library are constructed by combining        multiple basic logic gates, which is same as in normal CMOS        logic Cell library. All cells in RLCL logic library operate with        High Speed at transition time and with substantially reduced        leakage current in steady state. In another words, RLCL circuit        cells have significantly reduced leakage current without        significant loss in speed. These two features together make this        technology a compelling offering for implementation in modern        ICs.

All RLCL logic function gates constructed with general structure shownin FIG. 14A and more specific (one type of) embodiment FIG. 17 behave inthe same way as RLCL inverter of FIG. 16 and RLCL NAND2 gate of FIG. 18.

FIG. 19A shows another embodiment of implementation of the generalcircuit scheme of FIG. 14A. FIG. 19A is a variation in circuit levelimplementation from one shown in FIG. 17.

As stated earlier various sub-blocks of circuit functionalitiesrepresented in FIG. 14A can be merged together or divided into two ormultiple subsections. FIG. 19A shows a variant embodiment where thefunctional sub blocks of FIG. 14A are divided into multiplesub-sections.

As shown in FIG. 19A, various blocks of FIG. 14A (general constructionof RLCL functional gate) has been sub-divided and merged. There are twoPull up current control Circuits 15411 and 15431. Similarly there aretwo Pull up logic computation circuits 15412 and 15431, two Pull downLogic Computation Circuits 15413 and 15432, two Pull down currentcontrol circuit 15414 and 15432. The voltage translation circuits havebeen merged with other functions in block 15431 and 15432. Currentcontrol decision circuit 15415 is connected to Pull up current controlcircuit 1, 15411 and Pull down current control circuit 1, 15414 in thisembodiment. Four supply rails 15416, 15417, 15418 and 15419 are used inthis embodiment as in other embodiments of RLC circuits. Again one ortwo supply rails can be omitted depending on requirements of anapplication. For example, while using in address decoder of SRAM,Supply1 or Supply 2 may be omitted. Other connections of varioussub-blocks of this embodiment are as shown in FIG. 19A.

FIGS. 19B and 19C illustrate transistor level implementations of an RLCLINVERTER and an RLCL NAND2 functional gate respectively, accordingly tothe circuit scheme presented in block diagram in FIG. 19A.

FIG. 19B shows transistor level implementation of RLCL inverter as perthis embodiment (as shown in FIG. 19A). Pull up current control circuitis divided in two parts. The first part 15601 is the high speed Pull upCurrent Control Circuit that consists of a single High Speed PMOStransistor 15621. Its gate is connected to the output of “Currentcontrol Decision Circuit” 15605, its source is connected to Supply2(Vdd) and its drain is connected to the source of High Speed PMOS 15624.The second part of “Pull up current control circuit” is “Low Leakage”Pull up current control Circuit 15606. This functionality is merged withother functionalities in block 15606 that consists of a single LowLeakage PMOS transistor 15631. The source node of Low Leakage PMOStransistor 15631 is connected to Supply1 (Vddsp), its gate node isconnected to the input port “In” 15608 and its drain node is connectedto the output port “out” 15609 and to the drain of Low Leakage NMOS15607. “Pull up logic computation circuit” is also split in two parts.The first part 15602 is the High Speed Logic computation circuit thatconsists of a single High Speed PMOS transistor 15624 whose gate isconnected to the input port “In” 15608, source node is connected to thedrain of High Speed PMOS 15621 and the drain node is connected to theoutput port “Out” 15609. The second part of Pull up logic computationcircuit is merged with other functionalities in block 15606 that isimplemented with a single Low Leakage PMOS transistor 15631 as alreadydescribed in this paragraph. “Pull Down Logic Computation Circuit” isalso split in two parts, the first part 15603 is High Speed Pull DownLogic computation circuit implemented by a single High Speed NMOStransistor 15625 whose drain node is connected to the output port “Out”15609, gate node is connected to the Input port “in” 15608 and thesource node is connected to the drain node of High Speed NMOS transistor15627. Second part of the “Pull down Logic Computation Circuit” is theLow Leakage Pull Down Logic Computation Circuit that is merged withother functionalities in block 15607 that consists of a single LowLeakage NMOS transistor 15632. The drain node of this NMOS transistor15632 is connected to the output port “out” 15609, source node isconnected to Supply4 (Vsssp) and gate node is connected to the inputport “In” 15608. “Pull Down Current Control Circuit” is also split intwo parts—a high speed Pull Down Current control Circuit 15604 and a Lowleakage Pull down Current Control Circuit 15607 that is also merged withother functionalities. The High Speed Pull Down current control circuit15604 consists of a single High Speed NMOS transistor 15627 whose gateis connected to output of ‘Current control decision circuit” 15605, node15639. The second part of “Pull down Current Control Circuit” is the LowLeakage Pull down Current control Circuit” 15607 whose functionality ismerged with other functionalities of the gate. Its connectivity hasalready been described earlier in this same paragraph. Current Controldecision circuit 15605 consists of two Low Leakage CMOS inverters 15628and 15629. Both of these INVERTERS are simple CMOS inverters consistingof Low Leakage PMOS and Low Leakage NMOS transistors as shown in FIG.19D. Input of this block 15605 is the input to first Low LeakageINVERTER 15628 connected to the output Port “out” 15609. Output 15639 ofthis block is connected to the gates of High Speed PMOS and NMOStransistors 15621 and 15627.

Functioning of the RLCL INVERTER of FIG. 19B as per this embodiment isdescribed below:—

As in case of other RLCL embodiments, the input port “In” 15608 isdriven by another RLCL functional gate or a compatible circuit andtransitions from Vddsp to Vsssp and from Vsssp to Vddsp. When the Input“In” is LOGIC HIGH at Vddsp, Low Leakage NMOS transistor 15632 is ON andthe output port of the inverter 15609 is discharged to Vsssp (LOGIC LOW)through this Low Leakage NMOS transistor 15632. In this steady state theoutput node 15639 of “Current control decision circuit” 15605 is LOGICLOW at Vsssp which means High Speed NMOS 15627 is OFF and High SpeedPMOS 15621 is ON. This means node 15634 is charged to Vdd (not Vddsp)through ON PMOS 15621 and node 15635 is discharged to Vsssp through LowLeakage NMOS 15632 and ON NMOS 15625. Low Leakage PMOS 15631 is OFFbecause its gate is at Vddsp.

Furthermore, in this steady state High Speed Pull UP path from outputport 15609 to Supply2 (Vdd) though High Speed PMOS 15621 and 15624 isOFF because the High Speed PMOS 15624 is OFF with a negative gate-sourcevoltage. High Speed PULL DOWN path from output port 15609 to Supply3(Vss) through High Speed NMOS transistors 15625 and 15627 is also OFFbecause of OFF NMOS 15627 with ZERO gate-source voltage and Δv2 as itssource-drain voltage. Low Leakage PMOS 15631 is OFF with ZEROgate-source voltage and Low Leakage NMOS 15632 is ON discharging andholding the output port “out” 15609 to LOGIC LOW at Vsssp. Leakage inLow Leakage PMOS transistor is significantly small by definition.Leakage in high Speed PMOS 15624 is significantly small because ofnegative gate-source voltage which, as explained earlier, reduces theleakage of a High Speed MOS transistor significantly. The leakage inHigh Speed NMOS transistor 15627 is significantly smaller because ofvery small source drain voltage (Δv2), as in case of other embodimentsof FIG. 16 and FIG. 18.

Similarly when the Input Port “In” 15608 is in steady state at LOGIC LOWat voltage Vsssp, the output port “Out” 15609 is pulled high to Vddsp toLOGIC HIGH by Low Leakage PMOS 15631 which is ON because its gate nodeis connected to input port “In” 15608.

In this steady state the output node 15639 of “Current control decisioncircuit” 15605 is LOGIC HIGH at Vddsp because the output port “Out”15609 is at LOGIC HIGH. This means High Speed NMOS 15627 is ON and HighSpeed PMOS 15621 is OFF. This further means node 15635 is discharged toVss (not Vsssp) through ON High Speed NMOS 15627 and node 15634 ischarged to Vddsp through Low Leakage PMOS 15631 and ON High Speed PMOS15624. Low Leakage NMOS 15632 is OFF because its gate is driven by inputport “In” which is LOGIC LOW at Vsssp.

Furthermore in this steady state, High Speed Pull DOWN path from outputport 15609 to Supply3 (Vss) though High Speed NMOS 15625 and 15627 isOFF because the High Speed NMOS 15625 is OFF with a negative gate-sourcevoltage. High Speed PULL UP path from output port 15609 to Supply2 (Vdd)through High Speed PMOS transistors 15624 and 15621 is also OFF becauseof OFF PMOS 15621 with ZERO gate-source voltage and Δv1 as itssource-drain voltage. Low Leakage NMOS 15632 is OFF with ZEROgate-source voltage and Low Leakage PMOS 15631 is ON charging andholding the output port “out” 15609 to LOGIC HIGH at Vddsp. Leakagecurrent in Low Leakage NMOS transistor 15632 is significantly small bydefinition. Leakage in high Speed NMOS 15625 is significantly smallbecause of negative gate-source voltage. Negative gate source voltage,as explained earlier, reduces the leakage of a High Speed MOS transistorsignificantly. The leakage in High Speed PMOS transistor 15621 issignificantly small because of very small source drain voltage (Δv1), asin case of other embodiments of FIG. 16 and FIG. 18.

The RLCL inverter designed with the scheme as presented in FIG. 19A hassignificantly small leakage current in steady state.

During transition, the High Speed MOS transistors participate in theoperation making the RLCL function gate fast and usable in modern ICs asexplained in following sections:—

As explained in preceding paragraphs, when the input port “In” 15608 isat LOGIC HIGH the High Speed PMOS 15621 is ON but High Speed PMOS 15624is OFF. The ON High Speed PMOS 15621 makes the High Speed PULL up pathconsisting of PMOS 15621 and 15624 ready to transition at high speed.When input port “In” transitions from LOGIC HIGH (Vddsp) to LOGIC LOW(Vsssp), the High Speed PMOS 15624 turns ON thereby completing the PULLup path from output port “Out” 15609 to Supply2 (Vdd) immediately. LargePULL up transition current flows from Supply2 (Vdd) to the output portas result of this transition in the input port thus providing High SpeedPULL UP transition to output port “Out” 15609. This transition is alsoaugmented by the Low Leakage PULL UP transition path consisting of LowLeakage PMOS 15631. Once the output port “Out” 15609 crosses the logictransition threshold of Low Leakage inverter 15628 (which is when theoutput port has already crossed approximately Half Vdd voltage), theoutput of Low Leakage Inverter 15628 transitions LOW which causes theoutput of Low Leakage INVERTER 15629 (node 15639) to transition to LOGICHIGH to Vddsp, thereby switching OFF the High Speed PMOS 15621. LowLeakage PMOS 15631 still remains ON and pulls the output port “Out”15609 all the way up to Vddsp. After the transition, this RLCL gate isin steady state with the input port “In” held at LOGIC LOW at Vssspconsuming substantially smaller leakage current.

In opposite direction High Speed PULL DOWN transition of the output port“Out” 15609 is caused by the High Speed PULL DOWN path consisting ofHigh Speed NMOS transistors 15625 and 15627. When input port “In”transitions from LOGIC LOW (Vsssp) to LOGIC HIGH (Vddsp), the High SpeedNMOS 15625 turns ON thereby completing the PULL DOWN path from outputport “Out” 15609 to Supply3 (Vss) immediately. Large PULL DOWNtransition current flows from output port “Out” 15609 to Supply3 (Vss)thus providing High Speed PULL DOWN transition to output port “Out”15609. This transition is also augmented by the Low Leakage PULL DOWNtransition path consisting of Low Leakage NMOS 15632. Once the outputport “Out” 15609 crosses the logic transition threshold of Low Leakageinverter 15628 (which is when the output port has already crossedapproximately Half Vdd voltage), the output of Low Leakage Inverter15628 transitions HIGH which causes the output of Low Leakage INVERTER15629 (node 15639) to transition to LOGIC LOW to Vsssp, therebyswitching OFF the High Speed NMOS 15627. Low Leakage NMOS 15632 stillremains ON and pulls the output port “Out” 15609 all the way down toVsssp. After the transition, this RLCL gate is in steady state with theinput port “In” held at LOGIC HIGH at Vddsp consuming substantiallysmaller leakage current as explained earlier.

This way the RLCL inverter designed with the scheme shown in FIG. 19Aprovides High Speed functionality of a normal CMOS inverter withsubstantially reduced leakage.

FIG. 19C shows transistor level implementation of another (more complex)RLCL functional gate, NAND2, according to the scheme presented in FIG.19A. Steady state and transition behavior of NAND2 gate are similar tothe INVERTER of FIG. 19B, but NAND2 function gate provides thefunctionality of a Boolean 2 input NAND gate. As defined earlier NAND2Boolean function is defined such that it has 2 inputs and one output.The output is at LOGIC LOW only when both inputs of this Boolean logicgate are at LOGIC HIGH. In all other combinations of INPUTS, the outputis LOGIC HIGH. All can be seen by comparison of FIGS. 19B and 19C, allparts of RLCL NAND2 design are same as RLCL INVERTER of FIG. 19B exceptthe Pull UP Computation and Pull DOWN computation sections (5602, 5603,5606 and 5607) in FIG. 19C. These sections in FIG. 19C differ fromINVERTER of FIG. 19B only in computing the LOGIC functions as requiredby the NAND2 Boolean Logic function definition. Substantial leakagereduction in steady state and High speed transition behaviors remainsame.

A more detailed functionality of RLCL NAND2 gate as shown in FIG. 19C isas folllows:

As in case of INVERTER of FIG. 19B, the “Pull up logic computationcircuit” is divided in two circuit blocks 5602 and 5606 each consistingof High Speed and Low Leakage PMOS transistors respectively. Circuitblock 5606 in this implementation performs double function of “pull uplogic computation” and “voltage translation circuit”. Similarly, the“Pull down logic computation circuit” 5 is divided into two sub-blocks5603 and 5607 in this implementation each consisting of High Speed andLow Leakage NMOS transistors respectively. Block 5607 again performsdouble functions of “pull down logic computation” and “voltagetranslation circuit”. Blocks 5607 and 5607 also perform additional taskof holding output port to LOGIC LOW at Vsssp and LOGIC HIGH at Vddspafter the output has made the transition appropriately (according toBoolean function rule for NAND2 as defined earlier). The “currentcontrol decision circuit” 5605 in this implementation, works in exactlysame way as in the INVERTER of FIG. 19B. In this implementation, the LowLeakage MOS circuit and High Speed MOS circuits compute exactly samelogic for the functional gate separately but in exactly same way.However, the “pull up logic compute circuit” block 5606 and “Pull downlogic compute circuit” block 5607 are connected to Supply1 (Vddsp) andSupply4 (Vsssp) respectively while the Pull UP logic computation circuit5602 and Pull Down Logic computation Circuit 5603 are connected to Vddand Vss supplies, respectively through other MOS transistors.

As explained earlier, since the input ports In_1 and In_2 are driven byoutput of another RLCL or compatible circuit, the input ports transitionbetween voltages Vddsp and Vsssp. NAND2 Boolean functionality isperformed by High Speed PMOS transistors 5623 and 5624, High speed NMOStransistors 5625 and 5626 and Low Leakage PMOS transistors 5630, 5631and LOW Leakage NMOS transistors 5632 and 5633.

In one steady state, when both inputs In_1 and In_2 are LOGIC HIGH atvoltage Vddsp, output port 5609 (Out) is discharged to LOGIC LOW tovoltage Vsssp by Low Leakage NMOS transistors 5632 and 5633. The outputof “current control decision circuit” 5639 is LOGIC LOW and dischargedto voltage Vsssp, which causes High Speed NMOS 5627 to be switched OFFand High Speed PMOS transistor 5621 to be switched ON charging node 5634to Supply2 (Vdd). In this steady state condition, the High Speed NMOStransistor 5627 is OFF and has ZERO gate-source voltage but thedrain-source voltage is only Δv2 which is an order of magnitude smallerthan the supply voltage in practice. Hence the leakage in High SpeedNMOS 5627 is substantially lower than standard CMOS circuits. High SpeedPMOS transistors 5623 and 5624 have negative gate-source voltages andhence have substantially reduced leakage current from Vdd to output portor Vss or Vsssp. Leakage current through LOW Leakage and small MOStransistors 5630, 5631, 5632 and 5633 is substantially small bydefinition as explained earlier.

Similarly, in another steady state, when any or both of the input portsIn_1 and In_2 is LOGIC LOW at voltage Vsssp, the output port 5609 ispulled to LOGIC HIGH at Vddsp by one or both of the Low Leakage PMOStransistors 5630 and 5631. One or both of Low Leakage NMOS transistors5632 and 5633 are OFF and one or both of High Speed NMOS transistors5625 and 5626 are OFF. Thus, current pull-down paths from output port5609 to Vss or to Vsssp are cut OFF. In this steady state condition theoutput node 5639 of “current control decision circuit” 5605 is LOGICHIGH at voltage Vddsp which means High Speed PMOS 5621 is OFF and HighSpeed NMOS transistor 5604 is ON which pulls down node 5635 to Vss. Inthis steady state condition one or both of the High Speed NMOStransistors 5625 and 5626 have negative gate-source voltage thusreducing the leakage currents through them substantially. One or both ofthe High Speed PMOS transistors 5623 and 5624 are ON. Since output port5609 is pulled to LOGIC HIGH to voltage Vddsp, node 5634 also getscharged to Vddsp through one or both ON High Speed PMOS transistors 5623and 5624. This node then becomes source node for High Speed PMOStransistor 5621 whose gate is also at Voltage Vddsp. But since thesource-drain voltage of this PMOS transistor is only Δv1, the leakage ofthis PMOS will be substantially LOW because of small drain-sourcevoltage. As explained earlier Low Leakage PMOS and NMOS transistors5630, 5631, 5632 and 5633 are small in size and of low leakage bydefinition. Hence the leakage of entire circuit function issubstantially smaller than a normal CMOS circuit when the in this steadystate.

As in case of other RLCL functional gates already described, thebehavior of this gate is different during transition. Charging anddischarging of output port 5609 during transition happens through HighSpeed MOS transistors to provide high speed so that the technology canbe used commercially in modern ICs.

When both input ports In_1 and In_2 are at LOGIC HIGH (at voltageVddsp), the output port 5609 is at LOGIC LOW (at voltage Vsssp). If anyof the inputs transitions from LOGIC HIGH to LOGIC LOW (Vddsp to Vsssp),the output port (Out) transitions to LOGIC HIGH (to Vddsp) from LOGICLOW. Let's assume that Input Port In_1 transitions from LOGIC HIGH toLOGIC LOW. Before this transition, the output port is at LOGIC LOW(Vsssp), output of “Current control decision Circuit” 5605 is LOGIC LOWat voltage Vsssp, the High Speed PMOS 5621 is ON and High Speed NMOS5627 is OFF. When the Input In_1 transitions to LOGIC LOW (Vsssp), HighSpeed NMOS 5626 turns OFF and High Speed PMOS 5624 turns ON. Since HighSpeed PMOS 5621 is also ON, current from Vdd starts charging the outputnode 5609 through ON High Speed PMOS transistors 5621 and 5624. At thesame time Low Leakage NMOS 5633 turns OFF and Low Leakage PMOS 5630turns ON. This ON Low Leakage PMOS transistor starts charging the outputport 5609 to Vddsp. However, the charging of output port to Vddspthrough Low Leakage PMOS 5630 is too slow in comparison to charging ofthe output port to Vdd through High Speed PMOS transistors 5621 and5624. Once the output 5609 makes transition from LOGIC LOW to LOGICHIGH, the output of “Current control decision circuit” transitions toLOGIC HIGH to voltage Vddsp thereby causing the High Speed PMOS 5621 tobe tuned OFF. Output port 5609 is gradually pulled up to voltage Vddspby Low Leakage PMOS transistor 5630. This way the output of thisfunction gate makes fast transition from LOGIC LOW to LOGIC HIGH andthen settles into a substantially reduced leakage state automatically.Logic transition at output port is completed before the High Speed PMOStransistor 5621 is turned OFF because the process of turning OFF of thisPMOS 5621 is triggered only by the transition at the output port.

The output port makes transition from LOGIC LOW to LOGIC HIGH in exactlythe same way when both the Inputs In_1 and In_2 transition from LOGICHIGH to LOGIC LOW, except in this case, both High Speed PMOS transistors5624 and 5623 participate in charging of the output. Similarly both LowLeakage PMOS transistors 5630 and 5631 participate in charging of theoutput to Vddsp and holding the output to the voltage Vddsp in steadystate after transition at output port is completed.

Output transition from LOGIC HIGH to LOGIC LOW (from Vddsp to Vsssp)happens in similar way except in this case the output port is dischargedby pull down currents through High Speed and Low Leakage NMOStransistors 5625, 5626, 5632 and 5633. When both Input ports In_1 andIn_2 transition from LOGIC LOW to LOGIC HIGH or any of the themtransitions from LOGIC LOW to LOGIC HIGH while the other remained atLOGIC HIGH beforehand, both High Speed NMOS transistors 5625 and 5626turn ON. As explained earlier High Speed NMOS 5627 was already ON beforethis transition in steady state, the conduction path for pull downcurrent from output to Vss is completed. Output port 5609 hence startsdischarging quickly through the high speed Pull down path consisting ofHigh Speed NMOS transistors 5625, 5626 and 5627. Simultaneously, LowLeakage NMOS transistors 5632 and 5633 are also turned ON and conductionpath for pull down current from output port 5609 to Vsssp is completedthus discharging the output port to Vsssp. However, as expected, outputdischarge through High Speed NMOS transistors 5625, 5626 and 5627 thatare appropriately sized for speed, is much faster. Once the output port5609 makes LOGIC transition from LOGIC HIGH to LOGIC LOW, the outputnode 5639 of “Current control decision circuit” 5605 also transitions toLOGIC LOW after slight delay (the natural delay of two inverters 5628and 5629), thus turning OFF High Speed NMOS transistor 5627. LOGICtransition at output port 5609 is already completed before High speedNMOS 5627 turns OFF because the process of turning OFF of High SpeedNMOS 5627 starts only after output port 5609 has already made the LOGICtransition. Low leakage NMOS transistors 5632 and 5633 gradually pullthe output port 5609 to voltage Vsssp thus bringing the functional gateto its steady state of output being LOGIC LOW and holding the output inthis state till the transition occurs again because of appropriatechanges in input signals.

As shown in this FIG. 19D, Low Leakage PMOS transistor 5641 and LowLeakage NMOS transistor 5642 are represented symbolically by a LowLeakage inverter 5640. Two of these inverters make up “current controldecision circuit” 5605 in FIGS. 19C and 15605 in FIG. 19B. In actualimplementation, this schematic representation is exactly same as theschematic representation of “current control decision circuit” in FIG.19B. It can be easily understood that sizing of transistors in “currentcontrol decision circuit” will be chosen appropriately by designengineers in actual implementation according to speed, noise and otherperformance and implementation parameter requirements.

FIG. 19D shows transistor level implementation and connectivity of LowLeakage INVERTERS 15628 and 15629 of FIGS. 19B and 5628 and 5629 of FIG.19C. The low Leakage INVERTER of FIG. 19D, 5640 consists of the LowLeakage PMOS 5641 whose source is connected to Vddsp, drain is connectedto the output port and the drain of Low Leakage NMOS 6542 and Gate isconnected to the Input port and also to the gate of Low Leakage NMOS5642, and Low Leakage NMOS 5642 whose source is connected to Vsssp.

More complex and sophisticated comparator circuits can be used toconstruct the “current control decision circuit” in variations of thisdesign. Additionally, timing delay through “current control decisioncircuit” can be changed by many various methods including sizing, morestages, use of slower or faster MOS transistors, explicit or implicitloading of nets or MOS ports etc. This delay tuning will help incontrolling the ratio of current to Vdd/Vss and Vddsp/Vsssp, duration ofparticipation of high speed transistors in transitioning the output. Thesizing and ratio of sizes of High Speed and Low Leakage MOS transistorsis determined in actual implementation by design engineer based nvarious IC implementation requirements of performance, noise,reliability, leakage, speed etc.

As can be understood by people adept in this ART that all LOGICfunctions can be implemented (thus making a LOGIC function family) usingthe design scheme variation presented in FIGS. 19A, 19B and 19C whichthemselves are just one of the implementation of general schemepresented in FIG. 14A.

FIG. 20A illustrates yet another variation of general implementation ofthe general RLCL scheme presented in FIG. 14A. FIG. 20A representsdesign of RLCL function gates exactly like the ones in FIG. 17 exceptconnectivity of some of the sub-blocks have been reshuffled.

As compared to FIG. 17, the “Pull UP current control Circuit” and “Pullup logic computation circuit” have swapped places with each other inFIG. 20A. Similarly, as compared to FIG. 17, the “Pull down currentcontrol Circuit” and “Pull down logic computation circuit” sub-blockshave swapped places with each other in FIG. 20A. Accordingly, the supplynodes 5710 (Vddsp) and 5711 (Vdd) are now connected to “Pull upcomputation circuit” 5701 in FIG. 20A. Similarly, Supply nodes 5712(Vss)and 5713 (Vsssp) are now connected to “Pull down logic computationcircuit” in FIG. 20. All other connections remain same as theconnections in FIG. 17.

The “current control decision circuit” is connected to output port ofthe cell (Out) 5707 in same way as in FIG. 17. Additionally it may beconnected to “Pull up logic computation and current control circuit”5701 “Pull up current control circuit” 5702, “Pull down current controlcircuit” 5703, “Pull down logic computation & current control circuit”5704. In transistor level implementation each of these blocks can besub-divided into multiple blocks or merged together with other blocks ofform any combination of merge and divide to provide the fundamentalfunctionality as described in FIG. 14A. As compared to FIG. 17,connectivity of various sub-blocks to each other and supply rails hassmall changes, but the number of supply rails is same as in FIG. 17 withexactly same voltage relationship.

The reshuffling of various blocks of FIG. 17 as shown in FIG. 20Aprovides various advantages in speed and performance at expense of noiseperformance and active power consumptions. For example thisimplementation may provide better speed because of re-distribution ofcurrent but will have slightly lower noise performance than theimplementation according to FIG. 17 or may have slightly higher activecurrent as compared to FIG. 17.

People adept in the art of VLSI circuit design make these tradeoffs aspart of their daily work based on various functional, speed, noise,active power, leakage power etc. parameters.

FIG. 20B shows yet another variation in connectivity and design ofsub-blocks as compared to FIG. 20A. FIG. 20B is similar to FIG. 20Aexcept some of the sub-blocks have been split in two parts. Thisfunctionality sub-division is similar to the functionality sub-divisionillustrated in FIG. 19B. Again, this variation of FIGS. 20A and 19B isjust another implementation of the general RLCL circuit scheme presentedin FIG. 14A.

FIG. 21 shows MOS transistor level implementation of RLCL NAND2functional gate according to embodiments presented in FIG. 20B. MOSimplementation according to circuit scheme shown in FIG. 20A is similar.

MOS transistor level implementation of FIG. 20B is very similar to oneshown and described in FIG. 19C with exception of swapping of some ofthe sub-blocks connectivity in the circuit. All parts consisting of LowLeakage transistors are exactly same as in FIG. 19C and also function inexactly same way as in FIG. 19C. All other parts of circuits consistingof High speed transistors also function in mostly same way as in FIG.19C with small difference. This difference is in the way how, “pull upcurrent control circuit” 5802 and “pull down current control circuit”5803 and nodes connected to these sub-blocks behave during transitions.Steady state behavior of this implementation is same as the RLCL NAND2gate described in FIG. 19C. In steady state, all High Speed transistorsare OFF. Leakage currents in all high Speed transistors aresubstantially smaller than a CMOS implementation because of negativegate-source voltage or because of very small source-drain voltage onHigh Speed MOS transistors that are OFF. Output of the functional gateis held at Vddsp or Vsssp by LOW Leakage PMOS or NMOS transistors inblocks 5806 and 5807 depending on the LOGIC at Input ports In_1 andIn_2.

During transitions High Speed MOS transistors are active and provideHigh switching current to achieve high speed transitions and after theoutput has transitioned the High Speed MOS path (PULL up or PULL DOWN asappropriate) turns OFF as controlled by the ‘Current control decisionCircuit” 5805. This operation is exactly same as in other variations ofRLCL circuit implementation described before.

For example, when input ports In_1 and In_2 both transition to LOGICHIGH at Vddsp or one of them transitions to LOGIC HIGH when the otherwas already at LOGIC HIGH at Vddsp, the output 5809 transition fromLOGIC HIGH to LOGIC LOW at high speed by Pull DOWN current through HighSpeed NMOS transistors 5824, 5825 and 5826 as appropriate for a NAND2functionality. Once output port (Out) 5809 has made transition fromLOGIC HIGH to LOGIC LOW, output node 5839 of “Current Control DecisionCircuit” 5809 transitions to LOGIC LOW at Vsssp as previously describedin reference to other embodiments of RLCL functional gates. This causesthe High Speed NMOS transistor 5824 to turn OFF and High Speed PMOStransistor 5823 to turn ON. The output 5809 is then pulled down to Vssspby PULL DOWN path consisting of Low Leakage NMOS transistors 5832 and5833. Similarly when one or both of the Input ports In_1 and In_2transition to LOGIC LOW at Voltage Vsssp, output port 5809 quicklytransitions to LOGIC HIGH to Vdd through High Speed PULL UP pathconsisting of High Speed PMOS transistors 5821 and/or 5822 and 5823.Once output port (Out) 5809 has made transition from LOGIC LOW to LOGICHIGH, output node 5839 of “Current Control Decision Circuit” 5809transitions to LOGIC HIGH at Vddsp as previously described in referenceto other embodiments of RLCL functional gates. This causes the HighSpeed PMOS transistor 5823 to turn OFF and High Speed NMOS transistor5824 to turn ON. The output 5809 is then pulled UP to Vddsp by PULL UPpath consisting of Low Leakage PMOS transistors 5830 and/or 5831. Theseevents are exactly same as in the embodiment of RLCL NAND2 functionalgate described in FIG. 19C.

There is a small difference though. Due to the special connectivity ofHigh Speed PMOS 5823, when output port 5809 is pulled DOWN to LOGIC LOWand node 5839 is also PULLED DOWN to LOGIC LOW, High speed PMOS 5823turns ON. This makes node 5840 discharge to a voltage that is a PMOSthreshold voltage above the voltage at output port 5809 at this exactmoment (and eventually to a voltage equal to Vsssp due to leakage if theoutput port 5809 doesn't switch again for long time). This is due tonatural electrical behavior of a PMOS transistor. This results in chargesharing between output node 5809 and node 5840. This charge sharingcreates small kink in the output node thereby slowing down the dischargeof output node 5809 slightly or causing small bump in the output nodethat jumps up slightly before discharging to Vsssp completely. Outputport 5809 is pulled down to Vsssp by current in Low Leakage Pull downpath through NMOS transistors 5832 and 5833. It should be noted thatthis doesn't cause any LOGIC glitch in the output port 5809 since theoutput has transitioned to LOGIC LOW successfully before this chargesharing action. Similarly, when output port 5809 is pulled UP to LOGICHIGH and node 5839 is also PULLED high to LOGIC HIGH, High speed NMOS5824 turns ON (while High Speed PMOS 5823 turns OFF). This makes node5841 charge to a voltage that is a NMOS threshold voltage below thevoltage at output port 5809 at this exact moment (This node 5841eventually charges to a voltage equal to Vddsp due to leakage if theoutput port 5809 doesn't switch again for long time). This is due tonatural electrical behavior of a MOS transistor. This results in chargesharing between output node 5809 and node 5841. This charge sharingcreates small kink in the output node thereby slowing down the chargingof output node 5809 slightly or causing small dip in the instantaneousvoltage of the output node that dips slightly before charging to Vddspcompletely. Output port 5809 is pulled up to Vddsp by current in LowLeakage Pull up path through PMOS transistors 5830 and/or 5831. Itshould be noted that this doesn't cause any LOGIC glitch in the outputport 5809 since the output has transitioned to LOGIC HIGH successfullybefore this charge sharing action takes place.

In driving long wires using this embodiment of RLCL implementation, wewould need to analyze this voltage bump to guarantee reliability. Propersizing of transistors in various blocks (in particular the ratio of LowLeakage and High Speed transistors) will mitigate or eliminate any noiseconcerns.

The connectivity described in this implementation reduces effect ofground bounce in source nodes of High Speed PMOS transistors when theoutput switches from LOGIC LOW to LOGIC HIGH (Vsssp to Vddsp) therebyincreasing the speed of transition. Therefore this implementation can beadvantageous for Speed.

Symbol of Low Leakage INVERTERS 5835 and 5836 are used again in thisFIG. 21 as in FIG. 19B and FIG. 19C, in “Current control decisionCircuit” 5805. MOS transistor level implementations of these Low Leakageinverters are exactly same as in FIG. 19D

FIG. 22 illustrates yet another implementation of the RLCL circuittechnology presented in FIG. 14A. This is a simpler schematicimplementation of RLCL circuits of FIG. 14A where all functionalities ofsub-blocks of FIG. 14A are merged into a “Pull up logic computation andvoltage translation with current control and current control decisioncircuits” 5901 and “Pull down logic computation and voltage translationwith current control and current control decision circuit” 5902. Thefour supply rails Supply1, Supply2, Supply3 and Supply4 are exactly sameas described with reference to FIG. 14A and in other embodiments of RLCLcircuit implementations. All basic logic functions are formed with oneor multiple input ports and one output port as in other implementations.Similarly, more complex functional circuits or cells are formed bycombining multiple basic functional gates (cells).

FIG. 23 illustrates a MOS transistor level implementation of an RLCLINVERTER function according to the scheme shown in FIG. 22. Thistransistor level implementation is same as the implementation in FIG. 15with some small modification, but the functioning of this structure isexactly same as explained earlier in detail for FIG. 15. When input port“In” transitions from LOGIC LOW at Vsssp to LOGIC HIGH at Vddsp the HighSpeed NMOS UN device 5942 and Low Leakage NMOS transistor 5944 are ON.The High Speed UN NMOS device 5942 pulls the output port 5929 down toVss with High Speed and Low Leakage NMOS device 5944 pulls the outputport 5929 down to Vsssp and keeps it there till the next transitionSimilarly, when input port “In” transitions from LOGIC HIGH at Vddsp toLOGIC LOW at Vsssp the High Speed PMOS UP device 5923 and Low LeakagePMOS transistor 5943 are ON. The High Speed UP PMOS device 5923 pullsthe output port 5929 UP to Vdd with High Speed and Low Leakage PMOSdevice 5943 pulls the output port 5929 UP to Vddsp and keeps it theretill the next transition. In this implementation, two new devices havebeen used. An UP device and a UN device—in which the UP device is aUni-directional High Speed PMOS transistor that conducts current only inone direction—source to drain when it is ON and conducts no current whenit is OFF. It also doesn't allow current from drain to source even whenit is ON. This UP device is turned on in the same way as a standard PMOStransistor (when gate is at lower voltage than source by more than thePMOS threshold voltage. There is never a current flow from drain tosource in this device. Similarly, the UN device is a Uni-directionalHigh Speed NMOS transistor that conducts current only in onedirection—drain to source when it is ON and conducts no current when itis OFF. This UN device is turned on in the same way as a standard NMOStransistor (when its gate node is more than an NMOS threshold above thesource node). There is never a current flow from source to drain in thisspecial High Speed NMOS device.

The inverter in FIG. 23 functions exactly the same way as the INVERTERshown in FIG. 15 whose functionality to fulfill high speed and lowleakage characteristics of RLCL technology is explained earlier.However, as explained earlier with reference to FIG. 15 there is ashortcoming in the implementation of INVERTER of FIG. 15 that there is ashort circuit current between Vdd and Vddsp when the input port “In” isat LOGIC LOW. Similarly the INVERTER of FIG. 15 has a short circuitcurrent between Vss and Vsssp when the input port “In” is at LOGIC HIGH.The shortcoming of the short circuit currents in INVERTER of FIG. 15 iseliminated in the INVERTER of FIG. 23 by use of these special MOSdevices UP and UN. When the input port “In” is LOGIC LOW at Vsssp, theoutput port 5929 is pulled to Vddsp by the Low Leakage PMOS 5921. Inthis condition, even through the gate of UP PMOS 5931 is tied to Vsssp,the transistor doesn't conduct current from Vddsp to Vdd because of itsuni-directional current conduction property. However, the UP PMOS 5931helps in transitioning the output to LOGIC HIGH by allowing high currentfrom Vdd to output port 5929 during transition of output port from LOGICLOW to LOGIC HIGH. Once the output has reached Vdd quickly it getspulled further UP by Low Leakage PMOS 5943. The drain node of UP PMOS5931 being pulled above Vdd makes the current ZERO in UP PMOS 5931.

Similarly, when the input port “In” is LOGIC HIGH at Vddsp, the outputport 5929 is pulled down to Vsssp by the Low Leakage NMOS 5944. In thiscondition, even through the gate of UN NMOS 5942 is tied to Vddsp thisNMOS transistor doesn't conduct current from Vss to Vsssp because of itsuni-directional current conduction property. However, the UN NMOS 5924helps in transitioning the output to LOGIC LOW by allowing high currentfrom output port 5929 to Vss during transition of output port from LOGICHIGH to LOGIC LOW. Once the output has reached Vss quickly it getspulled further DOWN by Low Leakage PMOS 5943 to Vsssp. The drain node ofUN NMOS 5941 being pulled below Vss makes the current ZERO in UN NMOS5941.

In the steady state conditions (when input port is held at LOGIC HIGH orLOGIC LOW), the high Speed UN NMOS and UP PMOS transistors have negativegate-source voltages hence the leakage in these High Speed UP and UN MOSdevices is substantially smaller. Leakage currents in Low Leakage MOStransistors are small by definition, thus the leakage current in thisINVERTER of FIG. 23 is substantially small. But the transition speed ofthe INVERTER is still governed by currents in High Speed MOS devices.Thus a high speed Reduced leakage RLCL INVERTER is realized.

FIG. 24 illustrates an implementation of a RLCL NAND2 functionalityusing UN and UP devices as per the circuit scheme of FIG. 22. Thisimplementation functions in the same way as the INVERTER of FIG. 23except it performs a NAND2 logic function while reducing the leakage ofthe functional gate by negative gate-source biasing as per the generalscheme of the circuit block diagram proposed in FIG. 14A.

FIGS. 25A-B illustrates examples of implementations of the UN and UPdevices, respectively, in semiconductor foundries. FIG. 25A shows animplementation of the UN device using a diode junction in series withthe drain of the NMOS transistor. This diode is shown schematically by6001 in FIG. 25A. On silicon, this diode is formed within the drain ofthe NMOS transistor by formation of a P+ diffusion 6010 in the N+diffusion of the drain as shown. Rest of the structures and formation ofUN NMOS device is exactly same as standard NMOS devices formed by thefoundry currently.

An alternative implementation of special NMOS transistor UN is shown inFIG. 25B. Instead of a diode, an NPN BJT transistor 6021 is in serieswith the drain terminal of the NMOS transistor. The implementation onsilicon of this NPN transistor is as shown by 6030. An N+ diffusion isformed within P+ diffusion 6031 which in turn is formed within N+ drain6032 of NMOS transistor.

UP PMOS transistors will be formed in the similar way as shown in FIG.25C and FIG. 25D. Like in UN NMOS, a diode 16001 is attached to thedrain terminal of PMOS device. On silicon such a device can be formed byforming N+ diffusion inside the P+ drain diffusion of the MOS transistoras shown in the FIG. 25C. An alternate method is to form a PNPtransistor 16021 in the drain terminal of the PMOS device instead of adiode as show in FIG. 25D by forming a P+ diffusion within a N+diffusion which is further formed by N+ diffusion in the P+ diffusion ofthe drain of PMOS device.

In operation, the diode or NPN/PNP transistors so connected to the drainof NMOS or PMOS transistors prevent current from flowing from the sourceto the drain for UN NMOS and prevent current flowing from drain to thesource for a PMOS device.

It is important to note that the source node for UP PMOS device isdefined as the diffusion terminal connected to the Vdd (or Vddsp oranother equivalent HIGH voltage supply node). Similarly the source nodefor UN NMOS device is defined as the diffusion terminal connected to theVss node (or Vsssp or another equivalent LOW voltage supply node. Forthese devices, a change in terminal voltage on source/drain doesn'tchange the designation of source/drain.

RLCL circuit technology can be used for reduction of leakage current andactive current and for improving performance in memory structures suchas SRAM (Static random access memory), DRAM (Dynamic Random AccessMemory), Flash memory etc. Use of RLCL circuit technology and itsapplication methods have been explained in following sections:

In CMOS, memory can be of many types such as “Static Random AccessMemory” (SRAM) or a “Dynamic Random Access Memory” (DRAM) or FlashMemory.

FIG. 26 shows the block level functional and structural block diagram ofa memory block. It consists of four sub-blocks including an “Addressdecoder” 6101, a “Control block” 6102, a “Sense Amp and IO” block 6103and an “Array of memory bit cells” 6104. Small variations may exist inimplementations that divide these blocks further in sub-blocks but at ahigh level FIG. 26 represents structural and functional partitioningfollowed by most memory implementations.

Memory bit Array (6104) occupies most of the area in a memoryimplementation and is also the most important part of the memoryimplementation. This array is made up of many mostly identical memorybit cells, with slight variations for edge cells. Edge cells are memorybit cells that form peripheral part of “memory bit array” 6104. Thenumber of memory bit cells in an IC is typically very large (can be inmillions). An array of thousands of memory bit cells in same memorystructure is common. Memory bit cells are commonly designed and providedby a manufacturing house (semiconductor foundry) because they are verysmall in size and special processing steps are performed by themanufacturers to keep their sizes small. Need for low cost and highperformance presents conflicting requirements on design of a memory bitcell which tend to reduce the memory bit cell size and demand moreperformance simultaneously. In CMOS ICs, in general, speed and size of acircuit component are inversely proportional to each other. Significantresources, time and efforts are spent on design and manufacturing ofmemory bit cell throughout the semiconductor industry, every year. Smalland high performance memory bit cell provides significant businessadvantage to any semiconductor manufacturing house over theircompetitors. Hence, having a smaller, faster or both memory bit cell canbe of high commercial value. Because of this reason, in modern times theResearch and Development efforts for design and manufacturing of memorybit cells is mostly lead and conducted by semiconductor manufacturingcompanies.

A memory bit and memory array store data for computation within systemor ASIC or any IC which is essential part of semiconductor IC and systemfunctionality. All other blocks shown in FIG. 26 exist to facilitatewriting into and reading from this array 6104. Most IC designers takeand use the memory bit cells provided by the manufacturer (Semiconductorfoundry) and assemble them in appropriate array size as per theirrequirements. All other blocks “Address decoder” 6101, “control block”6102, “Sense Amp &IO” 6103 are designed by IC design engineers based onthe memory bit cell size and characteristics provided by themanufacturing house (Semiconductor foundry).

There are some fundamental differences between memory bit cell for aDynamic Random Access Memory (DRAM) and a “static Random Access Memory”(SRAM) and Flash memory in CMOS process technologies. A DRAM memory bitcell is a capacitor with a MOS switch for access to the charge on thiscapacitor. Charge is stored on a capacitor and read through the MOSswitch. Each read destroys the charge of the memory bit cell and thecharge needs to be restored by active circuit tricks for the memory bitbefore it can be read again. DRAM memory bit cell also looses charge dueto leakage and the whole memory array needs to be refreshed periodicallyto compensate for the loss of charge due to leakage. In a refresh cycle,every memory bit cell is read. Read LOGIC value is written back to thesame memory bit cell immediately thus restoring the charge on memory bitcell to its healthy state. This is done for every memory bit cell in thearray. An SRAM bit cells consists of multiple MOS devices and retainscharge forever as long as the memory block is connected to a powersupply so that it does not require any refreshing. However, the DRAM bitcell is typically much smaller in size as compared to SRAM bit cell.Hence, DRAM memory ICs or DRAM memory blocks are much cheaper for agiven cost (in dollars or area) as compared to SRAM ICs or SRAM blocks.

Flash memory bits are special memory structures that retain chargestored within special PolySilicon structures even after the power supplyis disconnected. Thus Flash memory is a non-volatile memory.

SRAM is the fastest memory in CMOS, followed by DRAM and Flash memories.This is also the sequence for cost of memory per bit or memoryICs/blocks of same number of bits.

SRAM blocks and other memory circuits function in mostly same way in allcommonly implemented memories in Semiconductor industry. For convenienceSRAM functioning is explained in following sections with understandingthat all other memory blocks operate in similar way:—

With reference to FIG. 26, for efficiently utilizing resources in“address decoder” 6101, “control block” 6102 and “sense amp and IOblock” 6103, a group of memory cells are read and written simultaneouslyin the memory array 6104. The memory array 6104 is, therefore organizedin number of rows and columns. A whole row of memory bit cells iswritten and read simultaneously. A “word line” connects all memory bitcells in a row together and controls the accesses to them for read andwrite operations. A “bit line” connects all memory cells in a columntogether so as to provide a conduction path from bit cells to externalcircuitry through “Sense amp and IO” block 6103 for read and writeoperations. Because of this connection of all memory bit cells in acolumn to a single bitline, only one row can be written or read at onetime and only one of the read or write operation can take place at onetime using this bitline. Any subsequent reads or writes to the array canhappen only when the first operation has finished. To access two rowssimultaneously, two bitlines are required in which case the memory iscalled and designed to be a dual ported memory. In this way, if n numberrows are required to be read or written simultaneously, n bitlines arerequired in which case such a memory is called n-port memory. A bitlinemay consist of one wire (single ended bitline) or two wires(differential bitline). Differential bitlines (two wires for everybitline) is a common practice.

Timing and electrical behavior for reading and writing the memory bitarray is managed by the address decoder, control block and sense amp andIO block. These blocks are designed in such a way that an array of givenmemory bit cells is accessed for read and write, reliably,deterministically and with speed that memory is supposed to work at.

FIG. 27 illustrates more detailed connectivity and functional structureof SRAM memory implementation. As stated earlier this structure isapplicable to all other types of memories also.

As shown in FIG. 27 SRAM has four major blocks “address decoder” 6201,“control block” 6202, “Sense Amp and IO block” 6203 and “Memory bit cellarray” 6204. A simple and most commonly used design of a memory bit cellcalled 6T-bit cell (with 6 MOS transistors in one memory bit cell) 6223is also shown in FIG. 27. A set of wordlines 6211 each connect all cellsof one row. Differential bitlines 6212 are also shown in this example.One differential bit-line wires connect all cells of a column of memorybit cells together. The wordlines are driven by address decoder block6201 that further consists of address decoder and address driver gates6221. Both bitlines 6212 and Wordlines 6211 are used for read and writeoperations. During write operation, bitlines are driven by bitlinedriver which is part of a larger functional sub-block “Pre-charge,column MUX, Sense Amp & bit line driver 6222. During read operationbitlines are driven by the memory bit cell of the row being read.Complex timing and electrical behaviors are exhibited during memory readand write operations. A sophisticated timing and electrical behaviorcontrol mechanism is built by IC designers in address decoder, controlblock and Sense Amp & IO blocks to accomplish reliable read and writeoperations.

FIG. 28 illustrates a single bit cell of the RAM using reduced leakagecurrent technology. A detailed structure of a 6T SRAM memory bit cell6301 is shown. It consists of a pair of back-to-back connected invertersconnected to each other to form a bi-stable storage unit 6302. Abi-stable structure is one that can hold both logic ZERO and LOGIC ONEstates indefinitely unless a changing agent forces the state to changeThese two inverters are formed by PMOS transistors 6311, 6312 and NMOStransistors 6313, 6314 as shown in FIG. 28. A pair of pass transistorsconsist of NMOS transistors 6315, 6316 that connect the storage unit6302 to differential bit lines 6331 and 6332 respectively and also towordline 6330. An additional inverter 6303 made of PMOS transistor 6321and NMOS transistor 6322 is part of the address decode and wordlinedriver functionality shown in FIG. 27. This inverter is sized to drivethe long and resistive word line wire of the memory array. Bit lines6331 and 6332 are differential and form one logical bitline for read andwrite of the column in which this particular memory bit cell is placed.

In a common CMOS SRAM memory block, memory bit (storage unit) 6302 is abi-stable storage unit for this memory bit cell. Nodes 6333 and 6334work as nodes where LOGIC value are preserved indefinitely until changedby an external agent/event as long as power supply Vdd and Vss are aliveor ON. If node 6333 is driven to LOGIC HIGH, the inverter consisting ofPMOS 6312 and NMOS 6314 drives a LOGIC LOW at node 6334, that in-turndrives a LOGIC HIGH at node 6333 through inverter made of PMOS 6311 andNMOS 6313. To read the LOGIC value stores in this memory bit cell, firstboth the bitlines 6331 and 6332 are pre-charged (pulled UP) to Vdd bythe “Pre-charge, sense Amp & Bit line driver” unit 6304. Then thewordline 6330 is driven to LOGIC HIGH at voltage Vdd by the wordlinedriver 6303. Pre-charge action is terminated before switching ON thewordline. Bitlines 6331 and 6332 get connected to nodes 6331 and 6334respectively through pass transistors 6315 and 6316 that are now ONbecause of Word Line being pulled UP to Vdd. Let's assume that node 6333was at LOGIC HIGH (means at voltage Vdd) and node 6334 was at LOGIC LOW(means Vss). Then the bitline 6331 will remain pre-charged to Vdd whilebitline 6332 starts discharging to Vss through Pull down path inside thememory bit cell formed by NMOS transistors 6316 and 6314, after WordLine is Pulled UP to Vdd. A difference in voltage develops between thetwo bitlines which is correctly interpreted by the special circuit blockcalled SENSE AMP in “Pre-charge, sense Amp & Bit line driver” 6304block. For a LOGIC LOW at node 6333 and LOGIC HIGH at node 6334, bitline6331 is discharged by the pull down path inside the memory bit cellformed by NMOS transistors 6315 and 6313 while bitline 6332 remainspre-charged to Vdd. Again this voltage differential between the twowires of differential bit lines is senses correctly by the Sense Ampstructure within block 6304. During write operation, differential“bitline driver” of block 6304 drives bitline 6331 and 6332 toappropriate differential LOGIC values and voltages when wordline 6330 isON. Since the memory bit cell transistors are small and weak their LOGICVALUES are forcefully overwritten by strong bitline drivers of block6304.

Since many memory bit cells are connected to a bitline (single ended ordifferential), they have very high capacitive load. Also there are manyrows in a memory array, so the bitlines are long and skinny thereforealso very resistive. For high speed, NMOS transistors 6313, 6314 andpass transistors (also NMOS transistors) 6315 and 6316 need to providehigh current during read operation. Unfortunately, high current requireslarge sizes of these NMOS transistors, which makes a memory bit celllarge. Large pass transistors 6315 and 6316 also increase load on thebitlines, which is connected to many bit cells in a column, therebyreducing the gain from increasing sizes of these transistors. Large bitsize increase the size of memory array in X or Y or both directionsthereby increasing resistances in bitlines, wordline or both therebyfurther mitigating the gain from increasing NMOS sizes in a memory bitcell. A larger pass transistors pair 6115 and 6116 also means largercapacitance on the word line 6330 which is connected to many cellswithin a row, which makes the word line also slower.

In addition to capacitive load of bit cells on them and resistances ofbitlines and wordline wires, the speed of memory read and write is alsonegatively impacted by leakage currents in the pass transistors 6315 and6316 of the memory bit cells. Assuming that the memory bit cell to beread has LOGIC LOW to be read on left hand side bitline 6331 (means theright hand side bitline 6332 would stay pre-charged to LOGIC HIGH) whilethe LOGIC VALUE stored on left hand side storage nodes (that isconnected to the left side bitline 6331 with NMOS pass transistors thatare OFF) of ALL memory bit cells in that column is LOGIC HIGH. Passtransistors of those memory cells that connect the memory bit cells tothe bitlines are OFF because their respective Word Lines are LOGIC LOWat Vss. But these pass NMOS transistors will be leaking to make the bitline stay at LOGIC HIGH. This means the left hand side bit linedischarge current provided by the memory bit being read, id fighting theleakage current of other memory bit cells that are not being read. Thememory bit cell being read needs to compensate the leakage current ofall other cells in that column that tends to charge the left hand sidebit line because the leakage current are pulling the left hand side bitline UP to Vdd. Thus the left hand side bitline will discharge muchslower than it would have if there was no leakage current. Similarly,because of this same assumption, the storage node in all memory bitcells on the right hand side are LOGIC LOW while the storage node of thememory bit cell being read is at LOGIC HIGH (to keep the right hand sidebitline 6332 charged to Vdd). This means the pass transistors of allremaining memory bit cells (that are not being read) are OFF but haveleakage currents that is discharging the right hand side bit lines toVss. In effect, leakage currents in pass transistors of memory bit cellsthat are not being read can reduce speed at which the memory array canbe read by reducing the differential voltage in the bit lines. Forexample if the memory bit cell to be read had LOGIC LOW to be placed atbitline 6331 and LOGIC HIGH at bitline 6332 and if all other cells inthe column were such that the leakage through their pass transistorswould charge bitline 6331 and discharge bitline 6332, then this willmean that to develop a required differential between the two bitlines6331 and 6332 will take more time as compared to the situation if thepass transistors were not leaking. A larger differential voltage betweenbitlines means a more reliable read of the data. Sense Amp circuits thatdetect the differential voltage between bitlines need certain minimumvoltage to function reliably. In modern process technologies, thisdifferential can be in range of 20 mv-to-70 mv or higher. Largerdifferential voltage in bit lines provides faster speed of SENSEAMPLIFIERS.

Leakage currents in pass transistors cause delay during write operationas well because of the same reason of leakage current through passtransistors that are supposed to be OFF. However, the problem is not assevere during WRITE as it is during read.

Many methods are currently available in industry though manufacturingsteps or gate length adjustments to reduce the leakage in the passtransistors. One such solution involves special manufacturing steps toincrease the Threshold voltage (Vt) of pass transistor 6315 and 6316 ofthe bit cell. This method, while reduces the leakage in the passtransistors, also make them slower thus making the read and writeoperation of the memory array slower thereby causing the same effect itattempts to mitigate. Another method involves using larger gate lengthdevices as NMOS pass transistors 6315 and 6316 in the memory bit cells.This method also makes the NMOS pass transistors 6315 and 6216 weakthereby causing the memory read and write operation to be slower.

In summary currently available methods of reducing leakage in the passtransistors of the memory bit cells are not as effective as desired.

Above explanation of memory read and write operation speed degradationdue to leakage in the access MOS transistors (in this case NMOS) appliesto all other type of memories (DRAM, FLASH memory etc) whether theaccess MOS transistor is PMOS or NMOS.

As it will be shown in later paragraphs, RLCL circuit technology helpsimprove speeds of read and write operations by reducing leakage throughthe pass transistors 6315 and 6316 that are OFF and/or also by enhancingcurrent in the pass transistors that are ON.

In addition to causing performance impact, static power consumptions dueto the leakage in memory bit cells is a big problem. Pass transistorscontribute to a significant percentage of total leakage current in thememory bit cells.

Leakage current in the memory is becoming worse in cost and speedparameters through generations as manufacturing technology progresses tonewer generations. This leakage power (or static power) is a big concernin modern ICs.

RLCL circuit technology reduces the leakage (static) power of thememory. In addition it also improves performance of the memory. This isachieved without needing changes in memory bit cell. This feature (ofreducing leakage power and improving performance of the memory withoutneed to modify the memory bit cell) of RLCL circuit technology is ofsignificant commercial advantage for IC implementation since the costlyprocess of designing/modifying memory bit cell is completely bypassed.

Following sections describe applicability of RLCL circuit technology inmemories in reducing leakage current and improving performance:—

With reference to FIG. 26, leakage is present in all blocks Addressdecode 6101, Control Block 6102, Sense Amp & IO 6103 and Memory bitarray 6104. However, the leakage current in memory array 6104 is themost significant portion of overall leakage current in the memory. In anormal CMOS memory of (any memory structure) represented by FIG. 26, allblocks except the memory array 6104 and Sense Amplifier circuits insideblock 6103 are normal CMOS logic gates. To implement memory array withRLCL technology all blocks that contain CMOS logic gates in a normalCMOS memory will get replaced by RLCL logic gates in memory with RLCLtechnology. Thus address decoder block 6101 will contain logic functionand timing circuits with RLCL technology. These logic gates areconstructed using one of the embodiments of RLCL logic gates followingthe general circuit scheme according to FIG. 14A. Sense Amplifier in the“Sense Amp & IO” block 6103 is replaced by RLCL sense Amplifier usingRLCL technology and circuit techniques. Thus using RLCL circuittechnology leakage current in “Address decoder” 6101, Control block 6102and “Sense Amp and IO” block 6103 is significantly reduced.

As described earlier, the memory bit used in the memory array can besame as the one provided by the manufacturing house (semiconductorfoundry), because developing new memory bit cell may be a very expensiveprocess. Even without changing the memory bit cell in the memory bitarray, the leakage of “memory bit cell array” 6104 is reducedsignificantly using RLCL circuit technology

FIG. 29 illustrates the leakage paths in a normal bit cell of a SRAMmemory. The schematic of FIG. 28 is reproduced in FIG. 29 with anemphasis of showing leakage currents in the memory bit cell. Fourcurrent leakage paths are shown that originate or terminate leakagecurrent in a memory bit cell. In a normal CMOS memory, when word line6430 is driven to Vss by the address decoder and word line driver (notshown in FIG. 29), this row is not selected for reading or writingoperation and all the bit cells in this ROW are supposed to beinaccessible. The Pass transistors 6415 and 6516 are OFF but areleaking. The amount of leakage current depends on the type and design ofthe Pass transistor NMOS and exact voltages on various nodes. Assumethat storage node 6433 is at LOGIC LOW (Vss) and storage node 6434 is atLOGIC HIGH (Vdd). Further assume that Bitline 6431 is NOT beingdischarged and is in pre-charge state (Vdd) which also means bitline6432 is being discharged by the bitcell that is being read (The bit cellbeing read is not shown in this Figure). As shown in FIG. 29, onecurrent leakage path 6441 exists from Vdd through pre-charged bitline(and the MOS transistor(s) pre-charging the bitline 6431 to Vdd), OFFNMOS 6415 and ON NMOS 6413. Since node 6433 is at voltage Vss, the NMOSpass transistor 6415 has maximum drain-source voltage and ZEROgate-source voltage and hence high leakage current through it. Anotherleakage current path 6442 exists from Vdd to Vss within the memory bitcell itself through OFF PMOS 6411 and ON NMOS 6413. In general the PMOSof memory bit cell is very small in width and of larger gate length thannormal gate length. Hence, this leakage current in OFF PMOS 6411 isrelatively smaller than any of the OFF NMOS in the memory bit cell.Since node 6433 is at Vss and node 6434 is at Vdd, NMOS transistor 6414is OFF. As shown in FIG. 29, yet another leakage current path 6443exists within the memory bit cell from Vdd to Vss through ON PMOS 6412and OFF NMOS 6414. This NMOS 6414 has high drain-source voltage. ThisNMOS is also much larger in comparison to both PMOS 6411 and 6412 Hence,leakage current through this NMOS transistor is much larger than theleakage current through any of the OFF PMOS transistors in the memorybit cell. Yet another leakage current path 6444 exists from Vdd of thememory bit through on PMOS 6412 and OFF NMOS transistor 6416 to thedischarging bitline 6432 (and hence to the NMOS of the bit cell that isbeing read and is discharging this bitline 6432). These are the fourprominent leakage current paths related to the memory bit cells. It isimportant to note that all bit cells in a memory bit array will beleaking current regardless of their status in the array unless theleakage is suppressed by doing something special in structure,functionality or working conditions. If the assumption about the stateof discharge and pre-charge between bit lines is reversed, the leakagepaths change their direction. Also the amount of leakage is different indifferent paths depending on the voltages at nodes within bit cells andbitlines and wordline.

Leakage current through pass transistors of the memory cell 6415 and6416 are significant part of total leakage current in the memory array.Since, there is large number of memory in most modern CMOS ICS, theleakage current in memory is large percentage of the total leakagecurrent of the IC even through the leakage in one memory cell issubstantially lower than most of the CMOS logic gates.

FIG. 30A illustrates a SRAM block implementation with RLCL technology.FIG. 30A is exactly same structure as in FIG. 26 except that “Addressdecoder” has been replaced by “RLCL Address decoder”, sub-block “SenseAmp and IO” has been replaced by “RLCL Sense Amp and IO” and “Controlblock” has been replaced by ‘RLCL Control Block”. In functionality theseblocks are exactly same as a normal CMOS SRAM memory of FIG. 26 but thenormal CMOS logic gates and circuits have been replaced by the RLCLlogic gates and RLCL circuit. RLCL logic gates and circuits are designedwith one of the embodiments and circuit topologies described in FIG. 14Aand explained in more detailed from FIG. 14A to FIG. 25D. As mentionedearlier, the SRAM bit cell remains same as in FIG. 26.

RLCL logic gates and RLCL circuit topologies used within sub-blocks“RLCL Address decoder” 16101, “RLCL Control block” 16102 and “RLCL SenseAmp & IO” 16103 result in substantially reduced leakage currents inthese circuit structures. Additionally, RLCL circuit technology resultsin substantially reduced leakage current in “memory array” 16104 also.

FIG. 30B shows circuit topology and design to achieve leakage currentreduction in memory array. For simplicity, only one memory bit has beenshown along with the last part of address decoder, called word linedriver. Instead of a normal CMOS inverter, an RLCL INVERTER has beenused as word line driver. One of the embodiments of RLCL INVERTER asexplained earlier can be used for the purpose. Choice of type of RLCLinverter will depend on speed, noise margin and active power consumptionrequirements. For simplicity of drawing a new symbol 6505 has been usedto represent the RLCL INVERTER. Rest of the address decoder sub-blockwill be constructed using RLCL circuits. 6504 is part of the wordlinedriver which is part of the address decoder section presented in FIGS.26 and 27 and FIG. 30A. Four power supply rails are used as in otherRLCL circuit topologies described earlier. Output of this RLCL inverteris the wordline 6530 that transitions from Vddsp to Vsssp (that are at“Vdd+Δv1” and “Vss-Δv2” respectively) as discussed earlier in thefunctionality of RLCL INVERTERs.

With RLCL technology the memory bit cell read and write works in thesame way as in a normal CMOS memory. When the wordline 6530 transitionsto Vddsp, NMOS pass transistors are ON and discharge one of the two bitlines 6531 and 6532 depending on whether node 6533 is at LOGIC LOW ornode 6534 is at LOGIC LOW. For memory application Δv1 can be ZERO orpositive (in range of 30 mv−200 mv). If Δv1 is ZERO the read and writecurrent through NMOS pass transistors 6515 and 6515 is same as in normalCMOS memory design. However, if Δv1 is positive, NMOS pass transistors6515 and 6516 get higher gate-source voltage than the normal CMOS memoryimplementation of FIG. 28. This increases the drive strength of passtransistors 6515 and 6516 thereby increasing the read current of Pulldown path of bitline that needs to discharge. Hence the bitline thatneeds to discharge does so faster than a normal CMOS memory, therebyimproving performance. If Δv1=ZERO then Vdd and Vddsp are at the samevoltage. In that case Vddsp or Vdd power supply rail can be eliminatedfor the word line driver inverter 6505. In the case where Δv1=ZERO, thismechanism of speed improvement is not present by use of RLCL technology.

However, a more subtle and more important performance improvementhappens by use of RLCL circuit technology.

When this ROW is not supposed to be read, the wordline is driven toLOGIC LOW to Vsssp (Vss-Δv2). Pass transistors 6515 and 6516 now havenegative gate-source voltage and hence they are OFF with significantlyreduced leakage currents through the OFF NMOS pass transistors 6515 and6516. With respect to FIG. 29, first and fourth leakage currents 6441and 6444 respectively are significantly reduced. Because of thisreduction in leakage currents, the discharge speed of bitline that isbeing discharged by one of the bit cells that is being read, doesn't getdegraded by leakage of bit cells in rows that are not being accessed.Because of this reduction in leakage current through pass transistors6515 and 6516, the bit line that is supposed to remain pre-charged,doesn't get erroneously discharged. These two effects result indeveloping faster bit line differential which results in ability for theSense AMPLIFIER in block 6503 to sense the bit line differential earlieror/and faster, which in turn improves performance. The reduction inleakage current through NMOS pass transistors also means that more bitcells can be attached to bit lines. This results in construction ofmemory with larger number of rows that can be read reliably which allowsconstruction of larger memory blocks which results in lower cost of thememory blocks. It is important to note that the leakage on bit linesfrom memory bit cells that are not being read, prohibits construction ofmemory blocks with large number of rows because the leakage of ROWS notbeing accessed will prohibit development of bitline voltage differentialreliably which will cause the memory block to become non-accessible forread in another words useless.

As explained earlier leakage through pass NMOS transistors in the bitcells of ROWs in the memory that are supposed to be inactive (notaccessed), is a major cause of degradation in memory read speed anddegradation of reliability of read operation. This leakage current alsoforces the memory structures to have less number of ROWs in the memorystructure than the case if the leakage current in these pass transistorsis significantly lower or ZERO. This means the leakage current in thepass transistors of the memory bits forces smaller memory blocks thanwhat is possible if this leakage current was ZERO (or small). Eachmemory block that is constructed needs to have its accompanying “AddressDecoder”, ‘Control Block” and “Sense Amp and IO” sub-blocks.Fundamentally, these sub-blocks are only overheads (for speed, area andfunctionality that are unnecessary extra cost and power consumption).This means when a large memory block of the chip needs to be dividedinto smaller sub-block the total overheads are higher than if one largememory block was constructed instead.

RLCL circuit topology allows larger SRAM memory blocks to be designed,implemented and manufactured thereby reducing the overhead of “addressdecoder”, “control block” and “Sense Amp and IO” blocks.

Thus by reducing leakage in NMOS pass transistors of the normal memorybit cell, RLCL technology allows design and implementation of largermemory blocks that are better in area, speed and power consumption. Thisis in addition to reduction in leakage power by reduction of leakage inall components and circuits in the memory block.

It is important to note that no changes in “memory bit cell” arerequired for these improvements to take place, which makes RLCLtechnology easily adoptable in implementing memories in ICs.

Use, advantages and importance of RLCL technology explained in precedingsections are not limited to SRAM memory. DRAM, Flash memory and otherCMOS based memory technology would realize similar speed, cost and powerimprovements by use of RLCL technology.

Similar modifications are required for realizing improvements inperformance and leakage in DRAM. DRAM bit cell will not require anymodifications. In case of DRAM memory also, the address decoder, controlblock, sense amp and IO sections are modified using RLCL circuittechnology to eliminate leakage in these sections as well as in memoryarray. In addition improved performance, improved area (that is lowerarea which means lower cost) and lower power consumption are realizedusing RLCL circuit technology. Similarly Flash memory can use RLCLtechnology in the same way as in SRAM blocks and be better in area,performance, cost and power consumption.

RLCL Circuit technology is also usable in CMOS dynamic circuits.

Dynamic circuit blocks are special CMOS circuit topologies used fordesign and implementation of very high performance circuits in ICs.Dynamic CMOS circuits provide very high speed in calculating Booleanlogic functions by speculatively computing one of the LOGIC states inadvance and by reducing capacitance in propagation paths. This circuittechnology in classical CMOS implementation is becoming extinct assemiconductor progress to modern smaller geometry CMOS because ofLeakage current in MOS transistors.

Using RLCL circuit technology, the limitation of dynamic circuits caneliminated thereby making dynamic circuits viable in modern technologiesto give performance advantage over normal CMOS static logic and RLCLstatic logic implementations.

FIG. 31A shows commonly used circuit structure of a CMOS dynamic Booleanlogic block. As shown in FIG. 31A, a dynamic Boolean logic blockconsists of small number of PMOS transistors (typically two) to PULL UPnode 6620 to Vdd and a clock gated pull down network to PULL DOWN node6620 to Vss. An inverter 6615 is connected between node 6620 and outputnode “Out” (6614). The output node 6614 is connected to gate node ofholding PMOS 6613. “Pre-charge” is a signal generated through specialtiming circuits (Design and use of such timing circuits is common in ICdesign Industry) from global “Clock” signal. The pre-charge signalswitches ON PMOS 6612 at time when the PULL down current path throughNMOS 6618 and “Pull Down Network” 6616 is OFF. The dynamic circuitevaluates its input and computes output accordingly in “evaluate” phasewhen Both “Pre-charge” and “Clock” nodes are driven to logic HIGH (Vdd).“Pre-charge” and “Clock” are input signals to this block. Their timingbehavior needs to be designed and implemented in such a way thatPre-charge signal goes from Vdd to Vss little later than Clock and goesfrom Vss to Vdd little earlier than the “Clock” signal. Such behavior iseasy to derive and is a common practice by engineers designing dynamiccircuits. It is not uncommon to use “Clock” input signal also as“Pre-charge” signal. Alternatively, “Pre-charge” signal can be generatedseparately from clock or from another source such that it providesfunctionality to PULL UP node 6620 by switching ON PMOS 6612 when thePULL DOWN current path through NMOS 6618 and “Pull down Network” 6616 isOFF. In this pre-charge state (when node 6620 is PULLED UP) the outputport “out” 6614 is LOGIC LOW at Vss. This switches ON PMOS transistor6613 which keeps node 6620 pre-charged to Vdd even if “Pre-charge”signal is removed. “Pull down Network” 6616 consists of NMOStransistors. PMOS and NMOS transistors used in this circuit block can below leakage or high performance transistors or a mixture of themdepending on design requirements.

FIG. 31B shows the simplest logic function designed as a dynamic circuitwhere the “Pull Down Network” 6616 consists of a single NMOS transistor6621 connected to only one input signal “In” (6622). Mostly, though,dynamic circuit blocks use more complex pull down network to implementcomplex Boolean logic function.

The dynamic CMOS circuits shown in FIGS. 31A and 31B have significantspeed advantage over static CMOS circuits because logic computationinvolves only NMOS that present much smaller capacitive loads on signalpropagation paths and have much larger drive currents. Dynamic circuitsgenerally consume more active power due to high activity on nodes.

With reference to FIG. 31A, when “clock” is driven to Vss (Logic LOW),“Pre-charge” signal is also driven to LOGIC LOW. This turns ON PMOS 6612while NMOS 6618 is OFF. PMOS 6612 charges the node 6620 to Vdd (LOGICHIGH). This drives logic “LOW” at output 6614 which in turn cause PMOS6613 to turn ON. Thus once charged, node 6620 is held at Vdd by PMOS6613 even if “Pre-charge” signal is driven to Vss. This is called‘Pre-charge” phase in dynamic circuit functioning. When “clock” isdriven high and also “Pre-charge” signal is already Vdd or driven to Vddbefore “Clock” signal” node 6620 will be discharged to Vss if the “PullDown Network” 6616 is conducting. If not-node 6620 is held at Vdd byPMOS transistor 6613. This is called “evaluation” phase for dynamiccircuits. The “Pull Down Network” 6616 conducts depending on the logicfunction computation designed in this network and the state of inputsignals. It must be noted that the PMOS transistor 6613 and the “PullDown Network” 6616 must be appropriately sized such that when the PullDown path is conducting, node 6620 is driven to Vss by overpowering theconduction of PMOS 6613. Once node 6620 is pulled down to Vss, theoutput node 6614 is driven to Vdd and PMOS 6613 is turned OFF. The fightbetween PMOS 6613 and “Pull Down Network” 6616 happens only duringtransition of node 6620 from Vdd to Vss.

The output of dynamic logic function of FIG. 31A is driven to LOGIC LOWin every clock cycle by pre-charging node 6620 to Vdd thus applying aLOGIC ZERO or LOGIC LOW at the output port 6614 of the gatespeculatively. The dynamic logic gate as shown in FIG. 31A, onlycomputes a LOGIC HIGH or LOGIC ONE at output port 6614 as function ofits input ports 6617. Logic ZERO or LOGIC LOW at output is driven bydefault through the pre-charge functionality.

As mentioned earlier, the viability and use of dynamic circuits has beenreducing almost to the extent of extinction in recent technology becauseof CMOS leakage current. The Severe negative effect of leakage currentis explained below:

Let's assume that the node 6620 has been pre-charged to Vdd means outputport 6614 is at LOGIC LOW (Vss). If the “Pull Down Network” 6616consists of High Speed NMOS transistors that have high leakage, during“evaluation” phase when “Clock” is LOGIC HIGH (at Vdd), leakage in PULLDOWN PATH consisting of “Pull Down Network” and NMOS 6618 may providesufficient current to discharge node 6620 enough to cause a LOGIC changeor a noise pulse in output node “Out” 6614, even if all the inputs areat LOGIC LOW. A high going pulse at output port “Out” 6614 or atransition to LOGIC HIGH only because of erroneous discharge of node6620 are bad. Both of these will result in malfunction of the nextdynamic logic function(s) whose input(s) is (are) driven by this output“Out” 6614. It must be noted that once discharges, node 6620 cannot bepulled UP again till the next “Pre-charge” state. This means that theLOGIC malfunction created by such temporary discharge of node 6620 maycreate a permanent and irrecoverable error in functionality and thusmake the IC malfunction. To eliminate this problem, the PMOS 6613 can bemade stronger such that even in worst adverse process, voltage,temperature or noise conditions (Noise on input signals or noise onpower supply rails) the output node 6620 is not discharged enough due toleakage or noise to cause LOGIC change or Noise pulse in output node6614. But this means that when node 6620 actually needs to getdischarged due to valid inputs and correct LOGIC function, the pull downpath consisting of “Pull Down Network” 6616 and NMOS 6618 will have tofight a stronger PMOS 6613 which degrades the speed of the dynamic gate.This degradation defeats the very purpose of adopting dynamic circuitgate in the first place. As stated earlier, dynamic circuits consumemore power because of high activity at various nodes. If they don'tprovide substantial speed improvement, they become impractical forcommercial ICs.

In summary leakage current is one of the biggest problems for dynamiccircuits as explained in previous paragraph—big enough to make themextinct in modern technologies.

RLCL technology reduces leakage drastically thereby eliminating theproblem of functional failure preserving the speed advantage of dynamiccircuits, thus making them useful and practical even in moderntechnologies.

FIG. 32 shows general scheme of connectivity for dynamic circuits usingRLCL circuit technology or RLCL dynamic circuits. FIG. 33 showsimplementation of the simplest RLCL dynamic functional gate.

General circuit scheme of CMOS dynamic circuits of FIG. 31( a) ismodified to make RLCL dynamic circuit as shown in FIG. 32A. Four powersupply rails are used instead of two as in all RLCL circuit schemes.Inverter 6615 of FIG. 31( a) is replaced by RLCL inverter 6710 in FIG.32A. RLCL inverter 6710 is the Reduced Leakage INVERTER using RLCLcircuit technology as per FIG. 14A for static CMOS gates as explained inthis invention and is implemented using one of the RLCL embodiments asillustrated in many figures from FIG. 14A to FIG. 25. PMOS transistors6702 and 6701 are connected to power supply rail Vddsp. “Pull DownNetwork” 6703 consists of preferably “High Speed” NMOS transistorsthough it can consist of any type of NMOS transistors. Input ports 6711of the dynamic gate are also inputs to the “Pull Down Network” 6703 andare driven by similar dynamic circuits or compatible circuits such thatthese nodes transition between supply rails Vddsp and Vsssp. Five newcircuit components are added—Low Leakage NMOS transistors 6706 and 6713and Low Leakage INVERTERS 6707 and 6708 and preferably High Speed NMOS6705 (preferably high speed, but it can be any other type MOStransistor). “Low Leakage” inverters 6707 and 6708 which, as shown inFIG. 32B, are normal CMOS Boolean INVERTER using “LOW LEAKAGE” PMOS andNMOS transistors connected to supply rails Vddsp and Vsssp. Gate of LowLeakage NMOS transistor 6713 is driven by “clock” input. Inverter 6707is designed such that its input switching threshold is lower than halfway between Vddsp and Vsssp. In practice, the extent of this thresholdmanipulation will be determined on many normal design considerations ofdynamic circuits commonly known to CMOS design engineers and commonlyprevalent in semiconductor industry. Such threshold manipulations areaccomplished by ration of PMOS and NMOS transistors and are also verycommon in semiconductor design industry. The output of inverter 6707 isconnected to gate of NMOS 6706 and input of inverter 6708. Output ofinverter 6708 is connected to the gate of NMOS 6705 which is in seriesof NMOS 6704 and “Pull Down Circuit” 6703, that constitute the Pull Downpath from node 6720.

FIG. 32B shows schematic representation of LOW Leakage Inverter used inFIG. 32A and is self explanatory.

FIG. 32A is only a sample configuration of dynamic circuit using RLCLtechnology. Other configurations, connectivity and choice of MOStransistors are possible using same general concept explained here andwithout deviating from these concepts.

FIG. 33 shows implementation of a simple function gate (a buffer) usingRLCL dynamic circuit topology of FIG. 32A. Functioning of RLCLtechnology in dynamic circuit is explained using functioning of thissimple dynamic circuit.

The “Pull Down Network” 6703 of FIG. 32A is replaced by a single NMOStransistor 6803 connected to a single input “In” 6811 in FIG. 33. In“Pre-charge” phase input signals “Pre-charge” and “clock” are at LOGICLOW at Vsssp. PMOS 6802 is ON and pulls UP node 6820 to Vddsp. The PULLDOWN path consisting of “Pull Down Network” 6803 and NMOS transistors6804 and 6805 is OFF because NMOS transistors 6804 is OFF. Similarly,the PULL DOWN path through NMOS 6806 and NMOS 6813 is OFF because NMOS6813 is OFF. In “Pre-charge” phase, Node 6820 is charged to Vddsp (LOGICHIGH), output node “Out” (6809) is driven to “LOGIC LOW” by RLCLINVERTER 6810 to Vsssp and PMOS 6801 is turned ON. Once node 6820 ispre-charged to Vddsp, the output of inverter 6808 is LOGIC HIGH and NMOS6805 is turned ON ready for “evaluate” phase. As in a normal dynamiccircuit, even if “Pre-charge” signal is pulled UP to “LOGIC HIGH” afterPMOS 6801 is turned ON, node 6820 remains charged to Vddsp though PMOS6801.

In this pre-charge phase, the PULL DOWN path consisting of NMOS 6803,6804 and 6805 has substantially reduced leakage because of negativegate-source voltage of NMOS 6804. Pull down path consisting of LowLeakage NMOS transistors 6806 and 6813 is OFF by definition because ofuse of Low Leakage transistors.

During evaluate phase, as in a normal dynamic circuit, “clock” input isdriven to LOGIC HIGH (to Vddsp or Vdd (Can be either)) causing NMOS 6804and 6813 to turn ON. If the “Pull Down Network” is conducting, that isif Input signals 6711 is LOGIC HIGH, then node 6820 will be dischargedto Vss through NMOS 6704 as in case of a normal dynamic circuit. Sincethe PULL DOWN path consisting of NMOS 6803, 6804 and 6805 consists ofpotentially high speed NMOS transistors, the pull down speed of node6820 is fast. In this case, the output of INVERTER 6807 will be drivento LOGIC HIGH to voltage Vddsp and NMOS 6806 will turn ON. Since LowLeakage NMOS 6813 is ON, the PULL down path from node 6820 to Vsssp isON and this path discharges node 6820 further down to Vsssp through ONNMOS transistor 6813 and 6806. This will satisfy the input conditionsfor RLCL INVERTER 6810 to function normally in reduced leakage mode asper RLCL technology and the output node “Out” (6709) is driven to LOGICHIGH to Vddsp by RLCL inverter 6810. This way—the transition of node6820 (and hence the transition of output “out” 6809) happens at highspeed through High Speed NMOS transistors. After node 6820 switches toLOGIC LOW, the output of Low Leakage inverter 6808 also switches toLOGIC LOW to Vsssp and causes the High Speed NMOS transistor 6805 toswitch OFF. Node 6820 is PULLED DOWN to Vsssp and held there throughPULL DOWN path consisting of Low Leakage NMOS transistors 6806 and 6813.Now, High Speed NMOS transistors 6803, 6804 and 6805 have ZEROgate-source voltage and Δv2 (very small compared to Vdd) drain-sourcevoltage. Low Leakage PMOS transistors 6801 and 6802 are OFF with ZEROgate-source voltage. The leakage current in this gate after transitionis very small because of negative gate-source voltage to OFF High SpeedMOS transistors or OFF Low leakage transistors.

Thus the LOGIC transition in this gate happens at high speed by use ofHigh Speed MOS transistors but after the transition, the gate settlesinto LOW Leakage state.

This operation is exactly same as the functioning of RLCL static gatesas explained in earlier sections. But for dynamic circuits, RLCL methodnot only reduces leakage current significantly but also performs a veryimportant task of making Dynamic CMOS circuits viable for modern CMOSprocess technologies.

With respect to FIG. 33, in “evaluation phase” if the input 6811 isLOGIC LOW at Vsssp, such that “Pull Down Network” is supposed to be OFFthen the NMOS transistors in “Pull Down Network” 6803 has negative “gatesource” voltage because its source is at Vss and its gate is driven byanother RLCL gate or compatible circuit, hence it is at Vsssp. Thismeans the leakage current in PULL DOWN path from node 6820 to Vssthrough NMOS 6803 and NMOS 6805 is substantially reduced. PULL DOWN PATHconsisting of Low Leakage NMOS 6806 and Low Leakage NMOS 6813 from node6820 to Vsssp is also OFF because output of INVERTER 6807 is LOGIC LOW(Vsssp) which keeps Low Leakage NMOS 6806 OFF. Leakage current in PULLDOWN path consisting of Low Leakage NMOS 6806 and 6813 is very low bydefinition because of the path consisting of Low Leakage NMOStransistors. Thus in such a case node 6820 is easily held at Vddsp byPMOS 6701. Now, the holding PMOS transistor 6801 can be weak and isstill able to hold node 6820 to Vddsp. Noise and malfunctioning issuesare eliminated because of elimination of leakage current in High SpeedPull Down path.

In “pre-charge” phase “clock” is LOGIC LOW, node 6820 is pulled high toVddsp and the PULL DOWN PATH though NMOS 6806 and 6813 is OFF. Once node6820 is charged to Vddsp in “pre-charge” phase the output of inverter6807 is LOGIC LOW which turns OFF NMOS 6806.

Because of reduced leakage in discharge path for node 6820 to Vss orVsssp by use of RLCL technology, dynamic circuit can be designed usingRLCL technology to retain their speed and area advantage in modernprocess technology over static circuits and can be used to design highspeed circuits.

Referring to FIG. 33, it can be noted that PMOS 6802 and 6801 are notrequired to be “Low Leakage” PMOS transistors but preferably they areso, since the Pull Down path consisting of “Pull Down Network” 6703 andNMOS 6705 has substantially reduced leakage current because of“Negative” gate source voltage on NMOS transistors used in the “PullDown Network” as explained.

As is obvious from this explanation and as will be recognized by peopleadept in the art of Semiconductor Circuit design, the scheme ofswitching OFF NMOS 6705 can also be implemented by changing the logicfunctions and re-arranging transistors in PULL DOWN PATH for variousdesign parameters such as smaller size or faster or less capacitive“clock” node etc.

FIG. 34A illustrates an alternative implementation of a dynamic bufferwith RLCL technology. As compared to FIG. 33, the two NMOS transistors6804 and 6805 of FIG. 33 are replaced by one NMOS transistor 6905 and a2 INPUT Low Leakage AND gate 6904. Clock input now is connected as inputof AND gate 6904, output of which drives the gate node of (preferably)High Speed NMOS 6905. Now the High Sped PULL DOWN path consists of onlytwo (preferably) High Speed NMOS transistors 6903 and 6905 (instead of 3NMOS transistors in FIG. 33).

People adept in the art of circuit design would recognize that both ofthese implementations (the one in FIG. 33 and the other in FIG. 34A)represent slight variation in exactly the same circuit concepts. Onlytransistors are reshuffled a little to make tradeoffs in speed, area,power consumption, complexity and ease of implementation. In this caseRLCL dynamic buffer of FIG. 34A is faster than the one in FIG. 33 butconsumes more area and presents more capacitive load on clock node whichincreases dynamic power and complexity of implementation.

FIG. 34B is schematic of the Low Leakage 2 input AND gate used in FIG.34A and is self explanatory.

RLCL dynamic buffers illustrate in FIGS. 33 and 34A use the samefundamentals of asserting negative gate-source voltage on High Speed(and hence High leakage) transistors. The fundamental concepts of RLCLtechnology as represented at high level in FIG. 14A and in more detailsin FIG. 14A to FIG. 35D, are used in dynamic circuits to reduced leakagecurrent in dynamic circuits and make them viable in modern semiconductorICs.

FIG. 35A and FIG. 35B illustrate the overall functioning of RLCL devicesin form of algorithm and flow charts. As shown in FIG. 35A, RLCL deviceis in reduced leakage state in steady state condition but ready totransition the output in opposite direction. When input signals changeto present the right conditions for logic to switch the output inopposite logic direction, high current flows in transition pathsconsisting of HIGH SPEED MOS devices. After completion of outputtransition, High Speed and High Leakage devices change state to lowleakage mode using negative gate-source voltage or very small drainsource voltage and the circuit enters the reduced leakage steady statecondition in opposite direction waiting for output to transition againwhen input signals change appropriately.

In more details an RLCL circuit is waiting in reduced leakage steadystate when output is LOGIC ZERO as indicate by state 7501 and 8001. Inthis state the circuit can wait indefinitely in reduced leakage currentstate. When input condition are appropriate to the logic to switch theoutput of RLCL gate in opposite direction and condition 7502 is met,High speed current flows from Vdd and Vddsp or from one of them tooutput, charging the output towards LOGIC ONE. Once the output hassafely transitioned to LOGIC ONE, High Speed MOS transistors changestate to reduced leakage state either because of active circuit isswitching off the High speed MOS components or the MOS components aredesigned with specific property of uni directional current. The outputis further pulled to up to Vddsp (still LOGIC ONE) by low leakage CMOScomponents. In this state again the circuit block enters the steadystate with reduced leakage current but ready to switch the output toLOGIC ZERO at high speed if the input changes again. This state is shownby state 7521 and 8021. Again when the input conditions change such thatthe output of the logic gate needs to transition to LOGIC LOW, highspeed MOS components conduct large discharge current from output to Vddand Vddsp or one of them. Again when the transition is completed, HighSpeed MOS components change state to reduced leakage state eitherbecause of active circuit is switching off the High speed MOS componentsor the MOS components are designed with specific property of unidirectional current. The output is further pulled down to Vsssp (stillLOGIC ZERO) by low leakage CMOS components. RLCL logic gate is now backto reduced leakage current state ready for transition in oppositedirection of state 7501 and 8001.

FIGS. 35A and 35B are similar except FIG. 34A indicates use of HighSpeed MOS components that can enter into LOW LEAKGE state automaticallybecause of operating condition while FIG. 35B indicates use of activecircuit to actively enforce such behavior in High Speed MOS components.

While the foregoing has been with reference to particular embodiments ofthe invention, it will be appreciated by those skilled in the art ofSemiconductor IC design and in particular that of Semiconductor Circuitdesign, that changes in these embodiment may be made without departingfrom the principles and spirit of the disclosure, the scope of which isdefined by the appended claims.

1. A low leakage current CMOS device that has one or more power rails,the device comprising: an input, an output and a logic function circuitthat receives an input signal on the input and generates an outputsignal on the output; a voltage translator that drives a voltage swingdifferential on the input and output or one of the input and output; acurrent control decision circuit that monitors and generates signals tocontrol flow of transition and leakage current and a current controlcircuit that has a deterministic voltage offset to the input voltageswing so that the device has reduced leakage current and controlstiming, magnitude and location of currents including transition currentand leakage current.
 2. The device of claim 1, wherein the currentcontrol circuit further comprises a pull up current control circuit anda pull down current control circuit.
 3. The device of claim 1, whereinthe logic function circuit further comprises a pull-up logic circuitcoupled to the pull up current control circuit and a pull-down logiccircuit coupled to the pull down current control circuit.
 4. The deviceof claim 1 further comprising a first voltage supply, a second voltagesupply, a third voltage supply and a fourth voltage supply wherein thefirst voltage supply delivers a larger voltage than the second voltagesupply and the third voltage supply delivers a larger voltage than thefourth voltage supply and first and second voltage supply delivervoltage larger than third and fourth voltage supply.
 5. The device ofclaim 1 further comprising a first voltage supply, a second voltagesupply, a third voltage supply and a fourth voltage supply wherein thefirst and fourth voltage supplies are connected to the voltagetranslator and the second and third voltage supplies are connected tothe current control circuit.
 6. The device of claim 5, wherein the firstvoltage supply further comprises a Vdd voltage added to a delta voltageand the fourth voltage supply further comprises a second delta voltagesubtracted from a Vss voltage.
 7. The device of claim 1, wherein thelogic function circuit is an inverter.
 8. The device of claim 1, whereinthe logic function circuit is a NAND2 logic gate.
 9. A low leakagecurrent CMOS device that has at least three power rails, the devicecomprising: an input, an output and a logic function circuit thatreceives an input signal on the input and generates an output signal onthe output; a voltage translator having a PMOS transistor and an NMOStransistor coupled to a first power rail and a second power rail, thevoltage translator driving a voltage swing differential on the input andoutput; a current control decision circuit that monitors and generatessignals to control flow of transition and leakage current; and a currentcontrol circuit having a PMOS transistor and an NMOS transistor coupledto a third power rail and a fourth power rail, the current controlcircuit having a deterministic voltage offset to the input voltage swingso that the device has reduced leakage current and controls timing,magnitude and location of currents including transition current andleakage current.
 10. The device of claim 9, wherein the PMOS transistorand an NMOS transistor of the current control circuit are each highspeed transistors.
 11. The device of claim 10, wherein the PMOStransistor and an NMOS transistor of the voltage translator are each lowleakage transistors.
 12. The device of claim 11, wherein the PMOStransistor of the current control circuit is a uni-directional highspeed PMOS transistor and the NMOS transistor of the current controlcircuit is a uni-directional high speed NMOS transistor.
 13. The deviceof claim 9, wherein the current control circuit further comprises a pullup set of PMOS and NMOS transistors and a pull down set of PMOS and NMOStransistors.
 14. The device of claim 13, wherein the logic functioncircuit further comprises a pull-up logic circuit coupled to the pull upcurrent control circuit and a pull-down logic circuit coupled to thepull down current control circuit.
 15. The device of claim 9, whereinthe first power rail has a Vdd voltage added to a delta voltage and thesecond power rail has a second delta voltage subtracted from a Vssvoltage.
 16. The device of claim 9, wherein the logic function circuitis an inverter.
 17. The device of claim 9, wherein the logic functioncircuit is a NAND2 logic gate.
 18. A memory with reduced leakage currentCMOS, comprising: an array of memory bit cells; a set of reduced leakagecurrent sense amplifiers using deterministic negative gate-sourcevoltage that sense bits of data on the array of memory bit cells; areduced leakage current address decoder using deterministic negativegate-source voltage that decodes an address used to one of read andwrite data to and from the array of memory bit cells; and a reducedleakage current controller using deterministic negative gate-sourcevoltage that controls the operation of the set of reduced leakagecurrent sense amplifiers and the reduced leakage current addressdecoder.
 19. The method of claim 18, wherein each of the set of reducedleakage current sense amplifiers and the reduced leakage current addressdecoder further comprises an input, an output and a logic functioncircuit that receives an input signal on the input and generates anoutput signal on the output; a voltage translator that drives a voltageswing differential on the input and output; a current control decisioncircuit that controls a voltage swing based on a negative gate-sourcevoltage applied to the voltage translator; and a current control circuitthat has a deterministic voltage offset to the input voltage swing sothat the device has reduced leakage current due to negative gate sourcevoltage.
 20. The memory of claim 18, wherein the reduced leakage currentaddress decoder comprises of reduced leakage current word line driver.21. The reduced leakage current address decoder of driver of claim 18where the word line driver further comprises an input, an output and alogic function circuit that receives an input signal on the input andgenerates an output signal on the output; a voltage translator thatdrives a voltage swing differential on the input and output; a currentcontrol decision circuit that controls a voltage swing based on anegative gate-source voltage applied to the voltage translator; and acurrent control circuit that has a deterministic voltage offset to theinput voltage swing so that the device has reduced leakage current dueto negative gate source voltage.
 22. The memory of claim 18, whereineach memory bit cell has a reduced leakage current pass transistorbecause of negative gate-source voltage applied by the word line driver.23. The memory of claim 19, wherein the current control circuit furthercomprises a pull up current control circuit and a pull down currentcontrol circuit.
 24. The memory of claim 23, wherein the logic functioncircuit further comprises a pull-up logic circuit coupled to the pull upcurrent control circuit and a pull-down logic circuit coupled to thepull down current control circuit.
 25. The memory of claim 19 furthercomprising a first voltage supply, a second voltage supply, a thirdvoltage supply and a fourth voltage supply wherein the first voltagesupply delivers a larger voltage than the second voltage supply and thethird voltage supply delivers a larger voltage than the fourth voltagesupply and supply1 and supply 2 are larger than supply 3 and supply4.26. The memory of claim 19 further comprising a first voltage supply, asecond voltage supply, a third voltage supply and a fourth voltagesupply wherein the first and fourth voltage supplies are connected tothe voltage translator and the second and third voltage supplies areconnected to the current control circuit.
 27. The memory of claim 26,wherein the first voltage supply further comprises a Vdd voltage addedto a delta voltage and the fourth voltage supply further comprises asecond delta voltage subtracted from a Vss voltage.
 28. A reducedleakage current CMOS dynamic circuit, comprising: a pull up circuitblock with at least one component connected to a pre-charge signal; aclocked pull down circuit block connected to at least one primary inputof the dynamic circuit; and a reduced leakage current inverter having aninput connected to the pull up circuit block and the clocked pull downcircuit block and an output connected to an output of the dynamiccircuit.
 29. The dynamic circuit of claim 28, wherein the reducedleakage current inverter further comprises an input, an output and aninverter logic circuit that receives an input signal on the input andgenerates an output signal on the output; a voltage translator thatdrives a voltage swing differential on the input and output; a currentcontrol decision circuit that monitors and generates signals to controlflow of transition and leakage current; and a current control circuitthat has a deterministic voltage offset to the input voltage swing sothat the device has reduced leakage current and controls timing,magnitude and location of currents including transition current andleakage current.
 30. The dynamic circuit of claim 29, wherein thecurrent control circuit further comprises a pull up current controlcircuit and a pull down current control circuit.
 31. The dynamic circuitof claim 30, wherein the inverter further comprises a pull-up logiccircuit coupled to the pull up current control circuit and a pull-downlogic circuit coupled to the pull down current control circuit.
 32. Thedynamic circuit of claim 30 further comprising a first voltage supply, asecond voltage supply, a third voltage supply and a fourth voltagesupply wherein the first voltage supply delivers a larger voltage thanthe second voltage supply and the third voltage supply delivers a largervoltage than the fourth voltage supply and first and second voltagesupply deliver voltage larger than third and fourth voltage supply. 33.The dynamic circuit of claim 30 further comprising a first voltagesupply, a second voltage supply, a third voltage supply and a fourthvoltage supply wherein the first and fourth voltage supplies areconnected to the voltage translator and the second and third voltagesupplies are connected to the current control circuit.
 34. The dynamiccircuit of claim 33, wherein the first voltage supply further comprisesa Vdd voltage added to a delta voltage and the fourth voltage supplyfurther comprises a second delta voltage subtracted from a Vss voltage.35. A method for constructing a low leakage current CMOS device that hasone or more power rails, an input, an output and a logic functioncircuit that receives an input signal on the input and generates anoutput signal on the output, the method comprising: driving, by avoltage translator connected to the logic function circuit, a voltageswing differential on one of the input and the output; controlling, by acurrent control decision circuit connected to the voltage translator andthe logic function circuit, the flow of transition and leakage current;and generating, by a current control circuit connected to the voltagetranslator, the current control decision circuit and the logic functioncircuit, a deterministic voltage offset to the input voltage swing sothat the device has reduced leakage current and controlling timing,magnitude and location of currents including transition current andleakage current.
 36. The method of claim 35, wherein generating thedeterministic voltage offset further comprises generating thedeterministic voltage offset by at least one of a pull up currentcontrol circuit and a pull down current control circuit.
 37. The methodof claim 36 further comprising providing a logic function circuitwherein the logic function circuit further comprises a pull-up logiccircuit coupled to the pull up current control circuit and a pull-downlogic circuit coupled to the pull down current control circuit.
 38. Themethod of claim 35 further comprising providing a first voltage supply,a second voltage supply, a third voltage supply and a fourth voltagesupply wherein the first voltage supply delivers a larger voltage thanthe second voltage supply and the third voltage supply delivers a largervoltage than the fourth voltage supply and first and second voltagesupply deliver voltage larger than third and fourth voltage supply. 39.The method of claim 35 further comprising providing a first voltagesupply, a second voltage supply, a third voltage supply and a fourthvoltage supply wherein the first and fourth voltage supplies areconnected to the voltage translator and the second and third voltagesupplies are connected to the current control circuit.
 40. The method ofclaim 37, wherein providing the logic function circuit further comprisesproviding an inverter.
 41. The method of claim 37, wherein providing thelogic function circuit further comprises providing a NAND2 logic gate.42. A method for constructing a CMOS based logic function gate, themethod comprising: providing an input receiver block that receives aninput to a logic function block; connecting a logic function block tothe input receiver block, the logic function block performing a logicfunction of the logic function gate based on the input; connecting anoutput driver block to the logic function block, the output driver blockdriving an output from the logic function block.
 43. The method of claim42 further comprising connecting a noise filter block to the inputreceiver block, the output driver block and the logic function block tofilter noise.
 44. The method of claim 42 further comprising providing avoltage translator that generates a voltage swing differential on theinput and the output, providing a current control decision circuit thatmonitors and generates signals to control flow of transition and leakagecurrent and providing a current control circuit that generates adeterministic voltage offset to the input voltage swing so that thelogic function circuit has reduced leakage current and controls timing,magnitude and location of currents including transition current andleakage current.
 45. The method of claim 44, wherein providing thecurrent control circuit further comprises providing at least one of apull up current control circuit and a pull down current control circuit.46. The method of claim 44, wherein providing a logic function blockfurther comprises providing one of a pull-up logic circuit coupled tothe pull up current control circuit and a pull-down logic circuitcoupled to the pull down current control circuit.
 47. The method ofclaim 44 further comprising providing a first voltage supply, a secondvoltage supply, a third voltage supply and a fourth voltage supplywherein the first voltage supply delivers a larger voltage than thesecond voltage supply and the third voltage supply delivers a largervoltage than the fourth voltage supply and first and second voltagesupply deliver voltage larger than third and fourth voltage supply. 48.The method of claim 44 further comprising providing a first voltagesupply, a second voltage supply, a third voltage supply and a fourthvoltage supply wherein the first and fourth voltage supplies areconnected to the voltage translator and the second and third voltagesupplies are connected to the current control circuit.
 49. A CMOSdevice, comprising: one or more high speed transistors each having agate connected to an input of the CMOS device and an output connected toan output of the CMOS device, the one or more high speed transistorsbeing connected to a first set of power rails; one or more low leakagetransistors each having a gate connected to the input of the CMOS deviceand an output connected to the output of the CMOS device, the one ormore low leakage transistors being connected to a second set of powerrails; the one or more high speed transistors having a negativegate-source voltage applied to them in a steady state to reduce leakagecurrent and the one or more low leakage transistors hold the steadstate.
 50. The CMOS device of claim 49, wherein the one or more highspeed transistors are a PMOS device and an NMOS device.
 51. The CMOSdevice of claim 49, wherein the one or more low leakage transistors area PMOS device and an NMOS device.